i2c Simulation Results

Simulation Results: i2c

10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.45 %

code
81.65 %

assert
96.19 %

func
81.50 %

line
96.38 %

branch
92.33 %

cond
85.23 %

toggle
89.66 %

FSM
44.64 %

Validation stages

V1		100.00%
V2		89.80%
V2S		100.00%
V3		0.00%

9/9 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	17.300s	1735.494us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	9.480s	1048.945us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.660s	19.233us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.670s	49.639us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.080s	439.891us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.420s	333.131us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.050s	94.103us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.670s	49.639us	1	1	100.00
	i2c_csr_aliasing	1.420s	333.131us	1	1	100.00

44/49 passed

89.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.890s	140.610us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	302.380s	10743.092us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	7.360s	273.229us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.750s	53.388us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	84.360s	56001.738us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	38.510s	1944.739us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.960s	118.543us	1	1	100.00
	i2c_host_fifo_fmt_empty	5.550s	350.869us	1	1	100.00
	i2c_host_fifo_reset_rx	2.600s	1022.914us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	153.210s	6990.377us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	7.190s	1090.043us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	1.550s	118.442us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.290s	434.657us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	26.770s	12939.738us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.880s	968.686us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	14.260s	2208.572us	1	1	100.00
	i2c_target_intr_smoke	3.760s	1965.042us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.790s	129.121us	1	1	100.00
	i2c_target_fifo_reset_tx	1.110s	229.959us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	29.980s	35293.952us	1	1	100.00
	i2c_target_stress_rd	14.260s	2208.572us	1	1	100.00
	i2c_target_intr_stress_wr	6.110s	5416.645us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	5.590s	6243.574us	1	1	100.00
target_clock_stretch				0	1	0.00
	i2c_target_stretch	11.870s	10013.421us	0	1	0.00
bad_address				1	1	100.00
	i2c_target_bad_addr	4.070s	6566.964us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	6.130s	10156.110us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.830s	997.139us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.980s	1021.374us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	7.360s	273.229us	1	1	100.00
	i2c_host_perf_precise	0.870s	447.432us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	7.190s	1090.043us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.020s	383.687us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.130s	610.347us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.670s	874.122us	1	1	100.00
	i2c_target_nack_txstretch	1.120s	2130.875us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.590s	1626.983us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.560s	455.320us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.610s	17.023us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.720s	18.731us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.840s	133.083us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.840s	133.083us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.660s	19.233us	1	1	100.00
	i2c_csr_rw	0.670s	49.639us	1	1	100.00
	i2c_csr_aliasing	1.420s	333.131us	1	1	100.00
	i2c_same_csr_outstanding	0.920s	35.505us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.660s	19.233us	1	1	100.00
	i2c_csr_rw	0.670s	49.639us	1	1	100.00
	i2c_csr_aliasing	1.420s	333.131us	1	1	100.00
	i2c_same_csr_outstanding	0.920s	35.505us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_sec_cm	0.860s	121.877us	1	1	100.00
	i2c_tl_intg_err	1.740s	593.485us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.740s	593.485us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	3.840s	392.376us	1
target_error_intr				1
	i2c_target_unexp_stop	1.160s	657.431us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	6.290s	571.967us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	28398247424580427737641152722131988410354974429329534189110565875747247889597	107	UVM_ERROR @ 140609724 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 140609724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	69263963680922892761701736042426599494536927791623974758490484714783731639682	167	UVM_ERROR @ 10743092122 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 10743092122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	88526562215834270045368027139916081459664514491834609143579716628537746495371	81	UVM_ERROR @ 434656786 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between UVM_INFO @ 434656786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
	i2c_target_stretch	60568430549502702957465031851776751738886484075719354687731765859874580522099	75	UVM_FATAL @ 10013421054 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! UVM_INFO @ 10013421054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])
	i2c_target_unexp_stop	4223872933584137462410941260057923264678390609546727931287373926496281396283	75	UVM_ERROR @ 657431492 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 20 [0x14]) UVM_INFO @ 657431492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
	i2c_target_hrst	115366035195915795392955180628944199180780241691874251231019561062864479223391	76	UVM_FATAL @ 10156109650 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! UVM_INFO @ 10156109650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	60053682303785807810406869999935932588379496158108617925642576841244799860024	89	UVM_ERROR @ 392376312 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 392376312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	112510736890640140169400620765511762900007416642972555281301297929168431987663	82	UVM_ERROR @ 571967379 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 571967379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---