Simulation Results: keymgr

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.38 %
  • code
  • 95.41 %
  • assert
  • 97.72 %
  • func
  • 63.02 %
  • line
  • 98.86 %
  • branch
  • 97.85 %
  • cond
  • 92.42 %
  • toggle
  • 97.23 %
  • FSM
  • 90.70 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.030s 353.753us 1 1 100.00
random 1 1 100.00
keymgr_random 4.080s 374.615us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.090s 14.755us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.840s 22.804us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 10.820s 3434.348us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 5.710s 491.968us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.880s 252.675us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.840s 22.804us 1 1 100.00
keymgr_csr_aliasing 5.710s 491.968us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 8.780s 3243.473us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.320s 58.058us 1 1 100.00
keymgr_sideload_kmac 1.440s 88.617us 1 1 100.00
keymgr_sideload_aes 2.340s 62.779us 1 1 100.00
keymgr_sideload_otbn 3.020s 90.061us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 9.610s 1004.549us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.070s 34.645us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.000s 51.231us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 1.690s 34.083us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 3.050s 139.949us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.810s 121.823us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 15.390s 416.521us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.940s 80.771us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.960s 23.175us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.400s 21.014us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.400s 21.014us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.090s 14.755us 1 1 100.00
keymgr_csr_rw 0.840s 22.804us 1 1 100.00
keymgr_csr_aliasing 5.710s 491.968us 1 1 100.00
keymgr_same_csr_outstanding 1.790s 102.599us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.090s 14.755us 1 1 100.00
keymgr_csr_rw 0.840s 22.804us 1 1 100.00
keymgr_csr_aliasing 5.710s 491.968us 1 1 100.00
keymgr_same_csr_outstanding 1.790s 102.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 6.960s 430.905us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_tl_intg_err 2.670s 217.743us 1 1 100.00
keymgr_sec_cm 6.960s 430.905us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 5.190s 284.531us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 5.190s 284.531us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 5.190s 284.531us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 5.190s 284.531us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 6.520s 956.324us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 6.960s 430.905us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 6.960s 430.905us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 2.670s 217.743us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 5.190s 284.531us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 8.780s 3243.473us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_csr_rw 0.840s 22.804us 1 1 100.00
keymgr_random 4.080s 374.615us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_csr_rw 0.840s 22.804us 1 1 100.00
keymgr_random 4.080s 374.615us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_csr_rw 0.840s 22.804us 1 1 100.00
keymgr_random 4.080s 374.615us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.070s 34.645us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.050s 139.949us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.050s 139.949us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 4.080s 374.615us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.460s 233.217us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 6.960s 430.905us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 6.960s 430.905us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 6.960s 430.905us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 1.920s 109.288us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.070s 34.645us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 6.960s 430.905us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 6.960s 430.905us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 6.960s 430.905us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.920s 109.288us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.920s 109.288us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 6.960s 430.905us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.920s 109.288us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 6.960s 430.905us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 1.920s 109.288us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 2.880s 111.067us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 23638257788289391754993803796424865633383360078962779966072257760792228769899 170
UVM_ERROR @ 111066769 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 111066769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---