Simulation Results: kmac

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.82 %
  • code
  • 88.65 %
  • assert
  • 97.58 %
  • func
  • 92.23 %
  • line
  • 97.30 %
  • branch
  • 95.25 %
  • cond
  • 93.66 %
  • toggle
  • 100.00 %
  • FSM
  • 57.02 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 32.500s 1725.132us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.050s 58.365us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.910s 16.712us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 6.810s 964.096us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.410s 183.477us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.830s 85.819us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.910s 16.712us 1 1 100.00
kmac_csr_aliasing 5.410s 183.477us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.780s 20.323us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.030s 81.912us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1224.380s 17306.277us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 471.830s 304307.059us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1136.630s 72438.211us 1 1 100.00
kmac_test_vectors_sha3_256 1642.570s 792556.977us 1 1 100.00
kmac_test_vectors_sha3_384 24.420s 6448.893us 1 1 100.00
kmac_test_vectors_sha3_512 589.600s 9584.148us 1 1 100.00
kmac_test_vectors_shake_128 1839.830s 145605.876us 1 1 100.00
kmac_test_vectors_shake_256 216.050s 5474.479us 1 1 100.00
kmac_test_vectors_kmac 2.260s 71.152us 1 1 100.00
kmac_test_vectors_kmac_xof 2.020s 77.476us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 170.240s 8592.801us 1 1 100.00
app 1 1 100.00
kmac_app 34.960s 992.762us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 128.080s 45134.180us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 10.780s 3906.556us 1 1 100.00
error 1 1 100.00
kmac_error 67.420s 2619.512us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 5.270s 1932.892us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 20.320s 10416.428us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 12.070s 1945.969us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 7.280s 491.649us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 21.190s 9409.342us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.450s 166.122us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 1133.110s 917558.827us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.840s 137.333us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.860s 30.755us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.980s 88.405us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.980s 88.405us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.050s 58.365us 1 1 100.00
kmac_csr_rw 0.910s 16.712us 1 1 100.00
kmac_csr_aliasing 5.410s 183.477us 1 1 100.00
kmac_same_csr_outstanding 1.180s 27.659us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.050s 58.365us 1 1 100.00
kmac_csr_rw 0.910s 16.712us 1 1 100.00
kmac_csr_aliasing 5.410s 183.477us 1 1 100.00
kmac_same_csr_outstanding 1.180s 27.659us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.510s 43.690us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.510s 43.690us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.510s 43.690us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.510s 43.690us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.740s 442.957us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_tl_intg_err 2.040s 554.758us 1 1 100.00
kmac_sec_cm 23.960s 5835.571us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.040s 554.758us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.450s 166.122us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 32.500s 1725.132us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 170.240s 8592.801us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.510s 43.690us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 23.960s 5835.571us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 23.960s 5835.571us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 23.960s 5835.571us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 32.500s 1725.132us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.450s 166.122us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 23.960s 5835.571us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 52.790s 3407.694us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 32.500s 1725.132us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 25.730s 2871.654us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)
kmac_sideload_invalid 80116820767897654287526508638019339906076724531581710545223087587763320526736 83
UVM_FATAL @ 10416427558 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x29225000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10416427558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---