Simulation Results: lc_ctrl

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.15 %
  • code
  • 85.21 %
  • assert
  • 94.13 %
  • func
  • 91.10 %
  • line
  • 97.13 %
  • branch
  • 93.82 %
  • cond
  • 79.73 %
  • toggle
  • 81.97 %
  • FSM
  • 73.40 %
Validation stages
V1
100.00%
V2
90.00%
V2S
71.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.970s 108.339us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.160s 137.657us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.010s 30.771us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.680s 52.902us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.900s 26.224us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.530s 30.041us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.010s 30.771us 1 1 100.00
lc_ctrl_csr_aliasing 0.900s 26.224us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.670s 473.160us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.120s 1086.090us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.120s 14.346us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.310s 65.983us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 5.550s 879.543us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.720s 584.360us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 5.550s 879.543us 0 1 0.00
lc_ctrl_prog_failure 2.310s 65.983us 1 1 100.00
lc_ctrl_errors 6.720s 584.360us 1 1 100.00
lc_ctrl_security_escalation 8.080s 374.924us 1 1 100.00
lc_ctrl_jtag_state_failure 11.350s 410.613us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.350s 328.865us 1 1 100.00
lc_ctrl_jtag_errors 21.160s 8473.573us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 1.820s 389.821us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.040s 222.733us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 17.180s 1082.650us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.060s 503.212us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.890s 229.049us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.170s 300.593us 1 1 100.00
lc_ctrl_jtag_alert_test 0.930s 105.350us 1 1 100.00
lc_ctrl_jtag_smoke 1.590s 155.084us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.310s 3613.138us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.350s 328.865us 1 1 100.00
lc_ctrl_jtag_errors 21.160s 8473.573us 1 1 100.00
lc_ctrl_jtag_access 7.620s 378.643us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.400s 1150.963us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.980s 113.728us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.830s 22.950us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 58.400s 15688.386us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.960s 63.802us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.890s 77.751us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.890s 77.751us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.160s 137.657us 1 1 100.00
lc_ctrl_csr_rw 1.010s 30.771us 1 1 100.00
lc_ctrl_csr_aliasing 0.900s 26.224us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.960s 84.136us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.160s 137.657us 1 1 100.00
lc_ctrl_csr_rw 1.010s 30.771us 1 1 100.00
lc_ctrl_csr_aliasing 0.900s 26.224us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.960s 84.136us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.580s 71.805us 1 1 100.00
lc_ctrl_sec_cm 6.410s 466.852us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.580s 71.805us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.120s 1086.090us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 5.550s 879.543us 0 1 0.00
lc_ctrl_sec_cm 6.410s 466.852us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 5.550s 879.543us 0 1 0.00
lc_ctrl_sec_cm 6.410s 466.852us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.550s 879.543us 0 1 0.00
lc_ctrl_sec_cm 6.410s 466.852us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.550s 879.543us 0 1 0.00
lc_ctrl_sec_cm 6.410s 466.852us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 5.550s 879.543us 0 1 0.00
lc_ctrl_sec_cm 6.410s 466.852us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.550s 879.543us 0 1 0.00
lc_ctrl_sec_cm 6.410s 466.852us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.550s 879.543us 0 1 0.00
lc_ctrl_sec_cm 6.410s 466.852us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 5.550s 879.543us 0 1 0.00
lc_ctrl_sec_cm 6.410s 466.852us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.080s 374.924us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.670s 473.160us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.310s 3613.138us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.190s 1113.186us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.190s 1113.186us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.010s 312.690us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.430s 289.117us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.430s 289.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 5.390s 56.696us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 102269504471702396856255853935271410927549464859237641359153351961204527176440 810
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 879543063 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 879543063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 60631957639526180352742985312642071175223125236705712484641294808041168698258 1101
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 410612814 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 410612814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 23219110377152024256338061296862354513805133958033949563290413848303195590711 5142
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 15688386430 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 15688386430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 32801104271496237320319107523164448322268779816262974836146739697874849031513 658
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 56695754 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 56695754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---