Simulation Results: lc_ctrl

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.64 %
  • code
  • 84.74 %
  • assert
  • 94.13 %
  • func
  • 90.04 %
  • line
  • 97.02 %
  • branch
  • 93.62 %
  • cond
  • 79.42 %
  • toggle
  • 81.02 %
  • FSM
  • 72.63 %
Validation stages
V1
100.00%
V2
87.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.250s 552.171us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.090s 29.598us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.920s 15.560us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.810s 169.835us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.370s 76.777us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.520s 251.903us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.920s 15.560us 1 1 100.00
lc_ctrl_csr_aliasing 1.370s 76.777us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 2.040s 83.551us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.180s 1411.131us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.010s 12.956us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.190s 322.823us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 5.190s 172.308us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.030s 200.094us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 5.190s 172.308us 0 1 0.00
lc_ctrl_prog_failure 2.190s 322.823us 1 1 100.00
lc_ctrl_errors 5.030s 200.094us 1 1 100.00
lc_ctrl_security_escalation 6.670s 610.913us 1 1 100.00
lc_ctrl_jtag_state_failure 11.350s 2976.889us 0 1 0.00
lc_ctrl_jtag_prog_failure 6.730s 2273.517us 1 1 100.00
lc_ctrl_jtag_errors 23.070s 5315.425us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.290s 430.173us 1 1 100.00
lc_ctrl_jtag_state_post_trans 16.450s 581.576us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.730s 2273.517us 1 1 100.00
lc_ctrl_jtag_errors 23.070s 5315.425us 1 1 100.00
lc_ctrl_jtag_access 3.130s 2264.825us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.300s 1455.944us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.590s 83.932us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.990s 153.295us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.810s 815.104us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.000s 188.432us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.130s 22.926us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.670s 388.036us 1 1 100.00
lc_ctrl_jtag_alert_test 0.960s 62.043us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.270s 2113.502us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.070s 23.553us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 65.060s 20637.682us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.190s 100.804us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.540s 192.882us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.540s 192.882us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.090s 29.598us 1 1 100.00
lc_ctrl_csr_rw 0.920s 15.560us 1 1 100.00
lc_ctrl_csr_aliasing 1.370s 76.777us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.920s 50.347us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.090s 29.598us 1 1 100.00
lc_ctrl_csr_rw 0.920s 15.560us 1 1 100.00
lc_ctrl_csr_aliasing 1.370s 76.777us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.920s 50.347us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.770s 492.077us 1 1 100.00
lc_ctrl_tl_intg_err 1.430s 62.744us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.430s 62.744us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.180s 1411.131us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 5.190s 172.308us 0 1 0.00
lc_ctrl_sec_cm 6.770s 492.077us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 5.190s 172.308us 0 1 0.00
lc_ctrl_sec_cm 6.770s 492.077us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.190s 172.308us 0 1 0.00
lc_ctrl_sec_cm 6.770s 492.077us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.190s 172.308us 0 1 0.00
lc_ctrl_sec_cm 6.770s 492.077us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 5.190s 172.308us 0 1 0.00
lc_ctrl_sec_cm 6.770s 492.077us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.190s 172.308us 0 1 0.00
lc_ctrl_sec_cm 6.770s 492.077us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.190s 172.308us 0 1 0.00
lc_ctrl_sec_cm 6.770s 492.077us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 5.190s 172.308us 0 1 0.00
lc_ctrl_sec_cm 6.770s 492.077us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.670s 610.913us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 2.040s 83.551us 0 1 0.00
lc_ctrl_jtag_state_post_trans 16.450s 581.576us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.620s 1166.950us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.620s 1166.950us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.800s 831.681us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.800s 351.029us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.800s 351.029us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 12.360s 491.778us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 113874011693435399521267396787747777299820145609170474007706001746501759307394 497
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 172308264 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 172308264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_state_post_trans 87385812638617435508647057527084126828895517458603337375473719220205640755660 255
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 83550859 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 83550859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 1225264114977816761757120482817618093362725370473582396542654236676274471401 1103
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2976889169 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2976889169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 67495933386534923278471417826077721822485659879960526229147856640186652022108 349
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 20637681865 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 20637681865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 12639200659298674548656102114094649478104568244472530282124981094544628751838 779
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 491777600 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 491777600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---