Simulation Results: otp_ctrl

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.88 %
  • code
  • 76.70 %
  • assert
  • 93.52 %
  • func
  • 66.42 %
  • line
  • 88.27 %
  • branch
  • 83.26 %
  • cond
  • 90.07 %
  • toggle
  • 78.48 %
  • FSM
  • 43.40 %
Validation stages
V1
100.00%
V2
88.00%
V2S
92.86%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.550s 56.347us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.290s 720.826us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.820s 244.953us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.520s 587.916us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 6.180s 1417.203us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.260s 1599.831us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.810s 149.176us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.520s 587.916us 1 1 100.00
otp_ctrl_csr_aliasing 3.260s 1599.831us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.210s 70.664us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.700s 474.707us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.610s 1254.207us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.720s 1399.453us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 7.240s 302.262us 0 1 0.00
otp_ctrl_check_fail 9.160s 450.489us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.310s 120.198us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 12.160s 875.035us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 9.640s 925.583us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 6.280s 527.732us 1 1 100.00
otp_ctrl_parallel_lc_esc 6.960s 362.168us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 11.170s 930.607us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 6.910s 1338.678us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 3.050s 193.241us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 27.810s 1387.962us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.280s 39.120us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.430s 2075.041us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.440s 160.959us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.440s 160.959us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.820s 244.953us 1 1 100.00
otp_ctrl_csr_rw 1.520s 587.916us 1 1 100.00
otp_ctrl_csr_aliasing 3.260s 1599.831us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.250s 86.575us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.820s 244.953us 1 1 100.00
otp_ctrl_csr_rw 1.520s 587.916us 1 1 100.00
otp_ctrl_csr_aliasing 3.260s 1599.831us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.250s 86.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_tl_intg_err 7.940s 652.998us 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 7.940s 652.998us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.290s 720.826us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.290s 720.826us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.960s 362.168us 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.960s 362.168us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.960s 362.168us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.960s 362.168us 1 1 100.00
otp_ctrl_macro_errs 6.910s 1338.678us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.960s 362.168us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.960s 362.168us 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.960s 362.168us 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.960s 362.168us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.960s 362.168us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.960s 362.168us 1 1 100.00
otp_ctrl_macro_errs 6.910s 1338.678us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.960s 362.168us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.960s 362.168us 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.720s 1399.453us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 9.160s 450.489us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 12.160s 875.035us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 12.160s 875.035us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 12.160s 875.035us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 12.160s 875.035us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 12.160s 875.035us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.290s 720.826us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 12.160s 875.035us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.290s 720.826us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 103.130s 19226.323us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.310s 120.198us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.290s 720.826us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.290s 720.826us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 6.910s 1338.678us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 8.090s 5935.069us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 21.340s 8162.187us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1308) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_background_chks 26841832855442648772370964762423656750434216236627487307635075292500019364949 8089
UVM_ERROR @ 302261616 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 302261616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 97292084856061066824990686137280181925307751652246641552056219006203921412961 5497
UVM_ERROR @ 450489109 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3936458823 [0xeaa19847] vs 3936458839 [0xeaa19857]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 450489109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 53765953342896782189794050566796348969248340555524868376678580234884481089688 4081
UVM_ERROR @ 1338677922 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 512 [0x200]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1338677922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 98507051099516129809682613152531964896360375252363892794341968632020129281025 371
UVM_ERROR @ 8162186610 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 8162186610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---