Simulation Results: pwm

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.62 %
  • code
  • 96.14 %
  • assert
  • 98.00 %
  • func
  • 95.71 %
  • block
  • 99.02 %
  • line
  • 99.28 %
  • branch
  • 98.27 %
  • toggle
  • 90.87 %
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwm_smoke 3.000s 4614.272us 1 1 100.00
csr_hw_reset 1 1 100.00
pwm_csr_hw_reset 1.000s 13.164us 1 1 100.00
csr_rw 1 1 100.00
pwm_csr_rw 1.000s 17.130us 1 1 100.00
csr_bit_bash 1 1 100.00
pwm_csr_bit_bash 4.000s 576.469us 1 1 100.00
csr_aliasing 1 1 100.00
pwm_csr_aliasing 2.000s 89.376us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwm_csr_mem_rw_with_rand_reset 2.000s 35.631us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwm_csr_rw 1.000s 17.130us 1 1 100.00
pwm_csr_aliasing 2.000s 89.376us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dutycycle 1 1 100.00
pwm_rand_output 31.000s 13465.943us 1 1 100.00
pulse 1 1 100.00
pwm_rand_output 31.000s 13465.943us 1 1 100.00
blink 1 1 100.00
pwm_rand_output 31.000s 13465.943us 1 1 100.00
heartbeat 1 1 100.00
pwm_rand_output 31.000s 13465.943us 1 1 100.00
resolution 1 1 100.00
pwm_rand_output 31.000s 13465.943us 1 1 100.00
multi_channel 1 1 100.00
pwm_rand_output 31.000s 13465.943us 1 1 100.00
polarity 1 1 100.00
pwm_rand_output 31.000s 13465.943us 1 1 100.00
phase 2 2 100.00
pwm_rand_output 31.000s 13465.943us 1 1 100.00
pwm_phase 30.000s 181796.883us 1 1 100.00
lowpower 1 1 100.00
pwm_rand_output 31.000s 13465.943us 1 1 100.00
perf 1 1 100.00
pwm_perf 30.000s 22758.555us 1 1 100.00
regwen 0 1 0.00
pwm_regwen 64.000s 60317.660us 0 1 0.00
stress_all 1 1 100.00
pwm_stress_all 117.000s 92812.927us 1 1 100.00
alert_test 1 1 100.00
pwm_alert_test 1.000s 13.439us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwm_tl_errors 3.000s 493.908us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwm_tl_errors 3.000s 493.908us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwm_csr_hw_reset 1.000s 13.164us 1 1 100.00
pwm_csr_rw 1.000s 17.130us 1 1 100.00
pwm_csr_aliasing 2.000s 89.376us 1 1 100.00
pwm_same_csr_outstanding 1.000s 58.333us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwm_csr_hw_reset 1.000s 13.164us 1 1 100.00
pwm_csr_rw 1.000s 17.130us 1 1 100.00
pwm_csr_aliasing 2.000s 89.376us 1 1 100.00
pwm_same_csr_outstanding 1.000s 58.333us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwm_sec_cm 2.000s 191.222us 1 1 100.00
pwm_tl_intg_err 3.000s 298.249us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwm_tl_intg_err 3.000s 298.249us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
heartbeat_wrap 1 1 100.00
pwm_heartbeat_wrap 39.000s 61771.313us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:217) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr pwm_reg_block.blink_param_* (addr=*)
pwm_regwen 28753830320367376943556398994766950019911682298124729828804548592615123321766 98
UVM_FATAL @ 60317660245 ps: (csr_utils_pkg.sv:217) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr pwm_reg_block.blink_param_2 (addr=0x7fcc48cc)
UVM_INFO @ 60317660245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---