Simulation Results: pwrmgr

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.89 %
  • code
  • 94.57 %
  • assert
  • 96.08 %
  • func
  • 97.03 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 94.48 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
52.94%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.660s 33.949us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.650s 35.812us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.620s 167.828us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.970s 135.620us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.920s 73.413us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.650s 37.933us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.620s 167.828us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 73.413us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.760s 138.901us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.760s 138.901us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.630s 28.779us 1 1 100.00
pwrmgr_lowpower_invalid 0.640s 84.389us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.730s 107.929us 1 1 100.00
pwrmgr_reset_invalid 0.730s 157.340us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.730s 107.929us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.690s 54.714us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.790s 244.342us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.680s 38.905us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.870s 679.025us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.620s 16.004us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.730s 69.708us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.730s 69.708us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.650s 35.812us 1 1 100.00
pwrmgr_csr_rw 0.620s 167.828us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 73.413us 1 1 100.00
pwrmgr_same_csr_outstanding 0.860s 80.618us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.650s 35.812us 1 1 100.00
pwrmgr_csr_rw 0.620s 167.828us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 73.413us 1 1 100.00
pwrmgr_same_csr_outstanding 0.860s 80.618us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_sec_cm 0.640s 7.199us 0 1 0.00
pwrmgr_tl_intg_err 0.620s 8.647us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.640s 7.199us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.640s 7.199us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.620s 8.647us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.480s 988.321us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.690s 54.714us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.810s 55.515us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.610s 30.948us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.640s 7.199us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.640s 7.199us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.640s 7.199us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.620s 79.412us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.550s 90.950us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.700s 150.322us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.620s 167.828us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.620s 167.828us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.720s 305.490us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 14.620s 6846.250us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
pwrmgr_escalation_timeout 57295633072203916268781900076314773085384992121150046440714391761545925503564 72
UVM_ERROR @ 305489802 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
UVM_INFO @ 305489802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_sec_cm 74994240739397523039507800843753504846320320459420657506883154355714996252429 75
UVM_ERROR @ 7199279 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 7199279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 66495472542088195067896760605163532857028047716942047555195503230602984291236 79
UVM_ERROR @ 8647244 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 8647244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---