Simulation Results: rom_ctrl

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.81 %
  • code
  • 99.26 %
  • assert
  • 96.80 %
  • func
  • 97.37 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 98.07 %
  • toggle
  • 99.49 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.210s 133.130us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.290s 130.900us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.160s 176.904us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.540s 986.585us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.380s 209.417us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.610s 132.045us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.160s 176.904us 1 1 100.00
rom_ctrl_csr_aliasing 3.380s 209.417us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.170s 373.052us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.620s 298.278us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.700s 174.789us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 9.440s 324.274us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.720s 1476.358us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.480s 556.747us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.260s 214.081us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.260s 214.081us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.290s 130.900us 1 1 100.00
rom_ctrl_csr_rw 4.160s 176.904us 1 1 100.00
rom_ctrl_csr_aliasing 3.380s 209.417us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.230s 475.514us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.290s 130.900us 1 1 100.00
rom_ctrl_csr_rw 4.160s 176.904us 1 1 100.00
rom_ctrl_csr_aliasing 3.380s 209.417us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.230s 475.514us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.240s 5300.189us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.130s 1948.292us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 186.820s 4930.476us 1 1 100.00
rom_ctrl_tl_intg_err 40.460s 2555.838us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 186.820s 4930.476us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 186.820s 4930.476us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.240s 5300.189us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.240s 5300.189us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.240s 5300.189us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.240s 5300.189us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.240s 5300.189us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 186.820s 4930.476us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 186.820s 4930.476us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.210s 133.130us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.210s 133.130us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.210s 133.130us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 40.460s 2555.838us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.240s 5300.189us 1 1 100.00
rom_ctrl_kmac_err_chk 6.720s 1476.358us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.240s 5300.189us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.240s 5300.189us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 69.240s 5300.189us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.130s 1948.292us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 186.820s 4930.476us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 214.950s 3573.841us 1 1 100.00

Error Messages

   Test seed line log context