Simulation Results: rom_ctrl

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.57 %
  • code
  • 98.05 %
  • assert
  • 95.49 %
  • func
  • 96.18 %
  • line
  • 99.46 %
  • branch
  • 98.18 %
  • cond
  • 93.02 %
  • toggle
  • 99.59 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.560s 569.578us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.630s 1583.630us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.930s 212.185us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.460s 628.512us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.440s 4166.616us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.880s 1926.416us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.930s 212.185us 1 1 100.00
rom_ctrl_csr_aliasing 6.440s 4166.616us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.650s 324.476us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.550s 289.884us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.010s 228.992us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 19.870s 2219.625us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 15.140s 547.437us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.180s 297.180us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.470s 545.249us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.470s 545.249us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.630s 1583.630us 1 1 100.00
rom_ctrl_csr_rw 5.930s 212.185us 1 1 100.00
rom_ctrl_csr_aliasing 6.440s 4166.616us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.650s 226.607us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.630s 1583.630us 1 1 100.00
rom_ctrl_csr_rw 5.930s 212.185us 1 1 100.00
rom_ctrl_csr_aliasing 6.440s 4166.616us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.650s 226.607us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 154.530s 5978.533us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 26.320s 9247.668us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_tl_intg_err 93.980s 351.917us 1 1 100.00
rom_ctrl_sec_cm 438.890s 1813.066us 0 1 0.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 438.890s 1813.066us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 438.890s 1813.066us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 154.530s 5978.533us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 154.530s 5978.533us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 154.530s 5978.533us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 154.530s 5978.533us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 154.530s 5978.533us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 438.890s 1813.066us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 438.890s 1813.066us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.560s 569.578us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.560s 569.578us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.560s 569.578us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 93.980s 351.917us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 154.530s 5978.533us 1 1 100.00
rom_ctrl_kmac_err_chk 15.140s 547.437us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 154.530s 5978.533us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 154.530s 5978.533us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 154.530s 5978.533us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 26.320s 9247.668us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 438.890s 1813.066us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 72.720s 4329.688us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 109809045077890946072745233170626366348003661807349570729664714374896095939481 105
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 7584417ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 7584417ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 7584417ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))