Simulation Results: rstmgr

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.76 %
  • code
  • 99.05 %
  • assert
  • 97.72 %
  • func
  • 96.52 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 97.78 %
  • toggle
  • 99.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.680s 254.416us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.980s 102.531us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.820s 66.322us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.470s 263.149us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.590s 240.952us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.020s 104.117us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.820s 66.322us 1 1 100.00
rstmgr_csr_aliasing 1.590s 240.952us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.130s 193.537us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.840s 442.191us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.930s 65.244us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.370s 833.378us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.370s 833.378us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.370s 833.378us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.370s 833.378us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 17.510s 7230.164us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.940s 81.124us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.890s 257.751us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.890s 257.751us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.980s 102.531us 1 1 100.00
rstmgr_csr_rw 0.820s 66.322us 1 1 100.00
rstmgr_csr_aliasing 1.590s 240.952us 1 1 100.00
rstmgr_same_csr_outstanding 1.560s 225.163us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.980s 102.531us 1 1 100.00
rstmgr_csr_rw 0.820s 66.322us 1 1 100.00
rstmgr_csr_aliasing 1.590s 240.952us 1 1 100.00
rstmgr_same_csr_outstanding 1.560s 225.163us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 24.380s 20356.733us 1 1 100.00
rstmgr_tl_intg_err 1.950s 694.123us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 24.380s 20356.733us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 24.380s 20356.733us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.950s 694.123us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.200s 137.819us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.200s 2466.211us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.200s 302.488us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 24.380s 20356.733us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.820s 66.322us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.820s 66.322us 1 1 100.00

Error Messages

   Test seed line log context