Simulation Results: rv_timer

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.14 %
  • code
  • 99.84 %
  • assert
  • 96.82 %
  • func
  • 91.76 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 99.38 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.560s 353.813us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.620s 26.973us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.750s 38.713us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.510s 142.682us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.840s 57.420us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.230s 29.511us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.750s 38.713us 1 1 100.00
rv_timer_csr_aliasing 0.840s 57.420us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.910s 101.990us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.860s 214.893us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 164.500s 269451.477us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 164.500s 269451.477us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.630s 5056.987us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.660s 10.463us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.810s 12.129us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.480s 202.097us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.480s 202.097us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.620s 26.973us 1 1 100.00
rv_timer_csr_rw 0.750s 38.713us 1 1 100.00
rv_timer_csr_aliasing 0.840s 57.420us 1 1 100.00
rv_timer_same_csr_outstanding 0.970s 16.019us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.620s 26.973us 1 1 100.00
rv_timer_csr_rw 0.750s 38.713us 1 1 100.00
rv_timer_csr_aliasing 0.840s 57.420us 1 1 100.00
rv_timer_same_csr_outstanding 0.970s 16.019us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_tl_intg_err 1.280s 284.938us 1 1 100.00
rv_timer_sec_cm 0.860s 69.495us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.280s 284.938us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.580s 123.725us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.910s 707.832us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 11.310s 7618.565us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*])
rv_timer_max 40637427881648777620764704924386606842089665628042278192366379989285847134832 72
UVM_ERROR @ 707831699 ps: (rv_timer_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
UVM_INFO @ 707831699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_random_reset 66021695992749569964506751010564150753452787647453359950953381193523480122902 72
UVM_FATAL @ 101989941 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7148ab04) == 0x1
UVM_INFO @ 101989941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done)
rv_timer_stress_all_with_rand_reset 40325354001535652060333369117162818778564308433184491745206576542670437083659 196
UVM_FATAL @ 7618564832 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 7618564832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---