Simulation Results: spi_device

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.58 %
  • code
  • 92.68 %
  • assert
  • 94.27 %
  • func
  • 69.79 %
  • line
  • 99.00 %
  • branch
  • 98.13 %
  • cond
  • 95.72 %
  • toggle
  • 87.57 %
  • FSM
  • 82.98 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 171.160s 113148.475us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.340s 148.338us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.220s 18.784us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 8.550s 2527.910us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.380s 217.534us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.170s 1925.555us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.220s 18.784us 1 1 100.00
spi_device_csr_aliasing 5.380s 217.534us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.790s 12.706us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.090s 26.635us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.950s 67.197us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.100s 24.257us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.880s 18.068us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.200s 359.964us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.200s 359.964us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 4.410s 1359.398us 1 1 100.00
spi_device_tpm_sts_read 0.970s 17.255us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 4.440s 833.575us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 5.370s 9212.638us 1 1 100.00
spi_device_flash_all 0.720s 73.505us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.850s 697.450us 1 1 100.00
spi_device_flash_all 0.720s 73.505us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.850s 697.450us 1 1 100.00
spi_device_flash_all 0.720s 73.505us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 0.720s 73.505us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.780s 1556.374us 1 1 100.00
spi_device_flash_all 0.720s 73.505us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.780s 1556.374us 1 1 100.00
spi_device_flash_all 0.720s 73.505us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.780s 1556.374us 1 1 100.00
spi_device_flash_all 0.720s 73.505us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.780s 1556.374us 1 1 100.00
spi_device_flash_all 0.720s 73.505us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.780s 1556.374us 1 1 100.00
spi_device_flash_all 0.720s 73.505us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 9.980s 3789.432us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 27.180s 13527.907us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 27.180s 13527.907us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 27.180s 13527.907us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 6.510s 2085.057us 1 1 100.00
spi_device_read_buffer_direct 4.430s 1111.729us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 27.180s 13527.907us 1 1 100.00
spi_device_flash_all 0.720s 73.505us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 0.720s 73.505us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 0.720s 73.505us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 6.860s 7075.143us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 6.860s 7075.143us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 171.160s 113148.475us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 66.440s 6782.848us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 48.310s 12462.118us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.870s 20.688us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.870s 63.475us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.470s 107.728us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.470s 107.728us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.340s 148.338us 1 1 100.00
spi_device_csr_rw 1.220s 18.784us 1 1 100.00
spi_device_csr_aliasing 5.380s 217.534us 1 1 100.00
spi_device_same_csr_outstanding 1.510s 102.905us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.340s 148.338us 1 1 100.00
spi_device_csr_rw 1.220s 18.784us 1 1 100.00
spi_device_csr_aliasing 5.380s 217.534us 1 1 100.00
spi_device_same_csr_outstanding 1.510s 102.905us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 12.840s 1268.697us 1 1 100.00
spi_device_sec_cm 1.260s 39.948us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 12.840s 1268.697us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 51.220s 33485.324us 1 1 100.00

Error Messages

   Test seed line log context