Simulation Results: spi_host

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.85 %
  • code
  • 95.02 %
  • assert
  • 95.21 %
  • func
  • 88.33 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 7.000s 833.186us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 18.573us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 40.246us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 85.510us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 30.566us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 27.989us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 40.246us 1 1 100.00
spi_host_csr_aliasing 1.000s 30.566us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 100.026us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 43.539us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 20.970us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 76.885us 1 1 100.00
spi_host_error_cmd 2.000s 32.585us 1 1 100.00
spi_host_event 25.000s 2030.044us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 113.624us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 113.624us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 113.624us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 17.000s 800.253us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 32.590us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 113.624us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 113.624us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 7.000s 833.186us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 7.000s 833.186us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 3.000s 509.349us 1 1 100.00
spien 1 1 100.00
spi_host_spien 10.000s 1807.396us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 283.000s 154052.546us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 139.585us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 76.885us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 17.259us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 39.155us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 175.177us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 175.177us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 18.573us 1 1 100.00
spi_host_csr_rw 1.000s 40.246us 1 1 100.00
spi_host_csr_aliasing 1.000s 30.566us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 23.768us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 18.573us 1 1 100.00
spi_host_csr_rw 1.000s 40.246us 1 1 100.00
spi_host_csr_aliasing 1.000s 30.566us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 23.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 1.000s 47.158us 1 1 100.00
spi_host_tl_intg_err 2.000s 269.591us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 269.591us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 164.000s 12940.599us 1 1 100.00

Error Messages

   Test seed line log context