Simulation Results: sram_ctrl

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.45 %
  • code
  • 89.33 %
  • assert
  • 95.65 %
  • func
  • 95.36 %
  • line
  • 97.40 %
  • branch
  • 94.95 %
  • cond
  • 92.41 %
  • toggle
  • 90.47 %
  • FSM
  • 71.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 39.310s 644.683us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.860s 62.089us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.680s 15.811us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.170s 192.699us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 39.629us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.090s 88.837us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.680s 15.811us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 39.629us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.500s 458.016us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.960s 587.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 437.670s 3818.298us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 302.060s 15157.975us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 52.650s 19857.368us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 408.110s 13326.068us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.760s 6427.235us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 216.580s 26173.153us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 30.750s 174.111us 1 1 100.00
sram_ctrl_partial_access_b2b 186.900s 72331.864us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 40.520s 668.193us 1 1 100.00
sram_ctrl_throughput_w_partial_write 31.860s 577.012us 1 1 100.00
sram_ctrl_throughput_w_readback 0.920s 46.055us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 160.890s 25298.955us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.710s 75.625us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 920.830s 7402.421us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.770s 26.083us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.970s 26.561us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.970s 26.561us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.860s 62.089us 1 1 100.00
sram_ctrl_csr_rw 0.680s 15.811us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 39.629us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.880s 18.458us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.860s 62.089us 1 1 100.00
sram_ctrl_csr_rw 0.680s 15.811us 1 1 100.00
sram_ctrl_csr_aliasing 0.680s 39.629us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.880s 18.458us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.850s 462.003us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.690s 1.834us 0 1 0.00
sram_ctrl_tl_intg_err 1.810s 157.555us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.690s 1.834us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.810s 157.555us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 160.890s 25298.955us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 160.890s 25298.955us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.680s 15.811us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 216.580s 26173.153us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 216.580s 26173.153us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 216.580s 26173.153us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.760s 6427.235us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.040s 50.915us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.850s 462.003us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.010s 107.690us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 39.310s 644.683us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 39.310s 644.683us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 216.580s 26173.153us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.690s 1.834us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.760s 6427.235us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.690s 1.834us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.690s 1.834us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 39.310s 644.683us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.690s 1.834us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 107.990s 1080.318us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 83854554320544628690464069940196224566067648555568280658947321306397829320791 96
UVM_ERROR @ 1833654 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 1833654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---