Simulation Results: sysrst_ctrl

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.58 %
  • code
  • 93.08 %
  • assert
  • 93.01 %
  • func
  • 70.65 %
  • line
  • 97.45 %
  • branch
  • 97.37 %
  • cond
  • 94.95 %
  • toggle
  • 100.00 %
  • FSM
  • 75.64 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.520s 2107.411us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.340s 2459.702us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 5.240s 2420.114us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.740s 2565.548us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 11.390s 6044.991us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 3.930s 2054.967us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 102.130s 38078.215us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.770s 2674.074us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.800s 2166.308us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 3.930s 2054.967us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.770s 2674.074us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 6.560s 32005.571us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 20.810s 39366.069us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 1.760s 3107.030us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 17.030s 476307.520us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.250s 2658.284us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.490s 2040.736us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.810s 3770.651us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.680s 2614.522us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.780s 5759.511us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 7.360s 31730.376us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 99.240s 186336.288us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.430s 2049.549us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.320s 2016.678us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 1.490s 3136.488us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 1.490s 3136.488us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 11.390s 6044.991us 1 1 100.00
sysrst_ctrl_csr_rw 3.930s 2054.967us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.770s 2674.074us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.700s 9272.298us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 11.390s 6044.991us 1 1 100.00
sysrst_ctrl_csr_rw 3.930s 2054.967us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.770s 2674.074us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.700s 9272.298us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 20.550s 22029.298us 1 1 100.00
sysrst_ctrl_tl_intg_err 7.700s 44830.341us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 7.700s 44830.341us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 9.000s 4780.785us 1 1 100.00

Error Messages

   Test seed line log context