Simulation Results: uart

 
10/12/2025 17:25:01 sha: 94ad61f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.52 %
  • code
  • 94.66 %
  • assert
  • 97.12 %
  • func
  • 64.77 %
  • line
  • 98.86 %
  • branch
  • 96.27 %
  • cond
  • 92.42 %
  • toggle
  • 91.10 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.110s 687.455us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.600s 38.493us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.620s 27.920us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.240s 139.609us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.700s 97.505us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.730s 34.305us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.620s 27.920us 1 1 100.00
uart_csr_aliasing 0.700s 97.505us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 49.870s 195861.452us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.110s 687.455us 1 1 100.00
uart_tx_rx 49.870s 195861.452us 1 1 100.00
parity_error 2 2 100.00
uart_intr 29.190s 20628.059us 1 1 100.00
uart_rx_parity_err 36.180s 154207.579us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 49.870s 195861.452us 1 1 100.00
uart_intr 29.190s 20628.059us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 346.690s 263806.525us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 39.770s 150097.612us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 36.630s 30312.070us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 29.190s 20628.059us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 29.190s 20628.059us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 29.190s 20628.059us 1 1 100.00
perf 1 1 100.00
uart_perf 431.650s 13548.207us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.810s 4829.943us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.810s 4829.943us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 35.050s 28740.155us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 5.860s 34335.500us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.900s 816.555us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 24.190s 4025.292us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 854.680s 173966.894us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 348.100s 478178.077us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.600s 33.963us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.600s 16.003us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.320s 34.724us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.320s 34.724us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.600s 38.493us 1 1 100.00
uart_csr_rw 0.620s 27.920us 1 1 100.00
uart_csr_aliasing 0.700s 97.505us 1 1 100.00
uart_same_csr_outstanding 0.660s 193.640us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.600s 38.493us 1 1 100.00
uart_csr_rw 0.620s 27.920us 1 1 100.00
uart_csr_aliasing 0.700s 97.505us 1 1 100.00
uart_same_csr_outstanding 0.660s 193.640us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.930s 304.534us 1 1 100.00
uart_tl_intg_err 0.900s 55.127us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.900s 55.127us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 40.980s 39320.815us 1 1 100.00

Error Messages

   Test seed line log context