Simulation Results: adc_ctrl

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.46 %
  • code
  • 97.10 %
  • assert
  • 95.95 %
  • func
  • 42.34 %
  • line
  • 99.05 %
  • branch
  • 98.64 %
  • cond
  • 95.91 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 5.910s 6018.333us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 3.270s 1374.202us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.700s 480.361us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 12.600s 18212.047us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.660s 958.391us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.060s 484.430us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.700s 480.361us 1 1 100.00
adc_ctrl_csr_aliasing 1.660s 958.391us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 544.180s 324959.291us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 237.020s 318000.710us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 221.250s 487935.122us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 38.100s 163398.442us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 111.490s 212568.043us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 77.410s 193647.197us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 274.360s 331965.688us 1 1 100.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 205.940s 2000000.000us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 5.560s 5137.873us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 60.910s 39345.339us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 114.710s 120973.742us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 648.710s 371040.111us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.830s 424.675us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.750s 519.896us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.510s 1324.611us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.510s 1324.611us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 3.270s 1374.202us 1 1 100.00
adc_ctrl_csr_rw 1.700s 480.361us 1 1 100.00
adc_ctrl_csr_aliasing 1.660s 958.391us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.740s 4472.405us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 3.270s 1374.202us 1 1 100.00
adc_ctrl_csr_rw 1.700s 480.361us 1 1 100.00
adc_ctrl_csr_aliasing 1.660s 958.391us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.740s 4472.405us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 2.770s 4090.829us 1 1 100.00
adc_ctrl_tl_intg_err 8.300s 4361.582us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 8.300s 4361.582us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 9.180s 24581.617us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
adc_ctrl_clock_gating 85014422528343218012117101237483542159862111786551750837906098771795089203599 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---