Simulation Results: aes

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.94 %
  • code
  • 88.22 %
  • assert
  • 97.75 %
  • func
  • 77.84 %
  • block
  • 89.68 %
  • line
  • 91.98 %
  • branch
  • 79.91 %
  • toggle
  • 97.99 %
  • FSM
  • 82.99 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 75.892us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 254.390us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 109.206us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 60.248us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 961.179us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 168.829us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 78.557us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 60.248us 1 1 100.00
aes_csr_aliasing 3.000s 168.829us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 254.390us 1 1 100.00
aes_config_error 2.000s 72.502us 1 1 100.00
aes_stress 3.000s 186.107us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 254.390us 1 1 100.00
aes_config_error 2.000s 72.502us 1 1 100.00
aes_stress 3.000s 186.107us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 186.107us 1 1 100.00
aes_b2b 2.000s 97.829us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 186.107us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 254.390us 1 1 100.00
aes_config_error 2.000s 72.502us 1 1 100.00
aes_stress 3.000s 186.107us 1 1 100.00
aes_alert_reset 2.000s 122.805us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 58.159us 1 1 100.00
aes_config_error 2.000s 72.502us 1 1 100.00
aes_alert_reset 2.000s 122.805us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 83.680us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 122.423us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 122.805us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 186.107us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 186.107us 1 1 100.00
aes_sideload 3.000s 78.200us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 144.203us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 10.000s 277.316us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 66.406us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 105.992us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 105.992us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 109.206us 1 1 100.00
aes_csr_rw 2.000s 60.248us 1 1 100.00
aes_csr_aliasing 3.000s 168.829us 1 1 100.00
aes_same_csr_outstanding 2.000s 94.996us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 109.206us 1 1 100.00
aes_csr_rw 2.000s 60.248us 1 1 100.00
aes_csr_aliasing 3.000s 168.829us 1 1 100.00
aes_same_csr_outstanding 2.000s 94.996us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 150.799us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 2.000s 90.161us 1 1 100.00
aes_control_fi 2.000s 60.560us 1 1 100.00
aes_cipher_fi 2.000s 77.694us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 103.246us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 103.246us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 103.246us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 103.246us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 107.844us 1 1 100.00
tl_intg_err 2 2 100.00
aes_tl_intg_err 3.000s 304.975us 1 1 100.00
aes_sec_cm 2.000s 1309.533us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 304.975us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 122.805us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 103.246us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 103.246us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 254.390us 1 1 100.00
aes_stress 3.000s 186.107us 1 1 100.00
aes_alert_reset 2.000s 122.805us 1 1 100.00
aes_core_fi 2.000s 258.437us 1 1 100.00
sec_cm_gcm_config_sparse 2 2 100.00
aes_config_error 2.000s 72.502us 1 1 100.00
aes_stress 3.000s 186.107us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 103.246us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 169.492us 1 1 100.00
aes_stress 3.000s 186.107us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 186.107us 1 1 100.00
aes_sideload 3.000s 78.200us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 169.492us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 169.492us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 169.492us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 169.492us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 169.492us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 186.107us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 186.107us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 2.000s 90.161us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 2.000s 90.161us 1 1 100.00
aes_control_fi 2.000s 60.560us 1 1 100.00
aes_cipher_fi 2.000s 77.694us 1 1 100.00
aes_ctr_fi 2.000s 64.064us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 2.000s 90.161us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 2.000s 90.161us 1 1 100.00
aes_control_fi 2.000s 60.560us 1 1 100.00
aes_cipher_fi 2.000s 77.694us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 77.694us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 2.000s 90.161us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 2.000s 90.161us 1 1 100.00
aes_control_fi 2.000s 60.560us 1 1 100.00
aes_ctr_fi 2.000s 64.064us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 2.000s 90.161us 1 1 100.00
aes_control_fi 2.000s 60.560us 1 1 100.00
aes_cipher_fi 2.000s 77.694us 1 1 100.00
aes_ctr_fi 2.000s 64.064us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 122.805us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 2.000s 90.161us 1 1 100.00
aes_control_fi 2.000s 60.560us 1 1 100.00
aes_cipher_fi 2.000s 77.694us 1 1 100.00
aes_ctr_fi 2.000s 64.064us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 2.000s 90.161us 1 1 100.00
aes_control_fi 2.000s 60.560us 1 1 100.00
aes_cipher_fi 2.000s 77.694us 1 1 100.00
aes_ctr_fi 2.000s 64.064us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 2.000s 90.161us 1 1 100.00
aes_control_fi 2.000s 60.560us 1 1 100.00
aes_ctr_fi 2.000s 64.064us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 2.000s 90.161us 1 1 100.00
aes_control_fi 2.000s 60.560us 1 1 100.00
aes_cipher_fi 2.000s 77.694us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 13.000s 1605.454us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 29660246824345019556146951400204948820691132259818300887172521102827378056866 134
UVM_ERROR @ 1605453759 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1605453759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---