Simulation Results: alert_handler

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.10 %
  • code
  • 93.12 %
  • assert
  • 98.23 %
  • func
  • 81.95 %
  • line
  • 99.72 %
  • branch
  • 99.79 %
  • cond
  • 95.12 %
  • toggle
  • 93.57 %
  • FSM
  • 77.42 %
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 12.440s 182.875us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 5.070s 43.828us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 5.610s 1199.333us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 150.760s 17779.104us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 67.600s 1751.433us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.220s 101.248us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 5.610s 1199.333us 1 1 100.00
alert_handler_csr_aliasing 67.600s 1751.433us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 73.310s 2215.084us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 11.170s 699.433us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1148.870s 201339.014us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 11.650s 277.296us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 12.440s 182.875us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 10.060s 302.479us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 15.420s 1042.830us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 6.120s 399.908us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 447.790s 8161.843us 1 1 100.00
alert_handler_lpg_stub_clk 1098.610s 631064.009us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 495.760s 17211.260us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 17.070s 2246.247us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 4.710s 94.911us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.350s 10.464us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 22.910s 1124.842us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 22.910s 1124.842us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 5.070s 43.828us 1 1 100.00
alert_handler_csr_rw 5.610s 1199.333us 1 1 100.00
alert_handler_csr_aliasing 67.600s 1751.433us 1 1 100.00
alert_handler_same_csr_outstanding 35.650s 703.886us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 5.070s 43.828us 1 1 100.00
alert_handler_csr_rw 5.610s 1199.333us 1 1 100.00
alert_handler_csr_aliasing 67.600s 1751.433us 1 1 100.00
alert_handler_same_csr_outstanding 35.650s 703.886us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 108.160s 1590.841us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 108.160s 1590.841us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 108.160s 1590.841us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 108.160s 1590.841us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 379.750s 8873.368us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_tl_intg_err 38.200s 2164.794us 1 1 100.00
alert_handler_sec_cm 9.300s 631.357us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 38.200s 2164.794us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 108.160s 1590.841us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 12.440s 182.875us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 12.440s 182.875us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 12.440s 182.875us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 12.440s 182.875us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 11.650s 277.296us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 447.790s 8161.843us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 11.650s 277.296us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1148.870s 201339.014us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1148.870s 201339.014us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.300s 631.357us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.300s 631.357us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.300s 631.357us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.300s 631.357us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 9.300s 631.357us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.300s 631.357us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.300s 631.357us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.300s 631.357us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 9.300s 631.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 64.560s 3261.653us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:595) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (* [*] vs * [*])
alert_handler_ping_timeout 76637297566003341484955334512328992080824786728989608490292524409172824474582 78
UVM_ERROR @ 399908034 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 399908034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 87688833644583187755619373924326954444451469540084708975424203282286315925131 137
UVM_ERROR @ 3261653188 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3261653188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---