Simulation Results: clkmgr

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.23 %
  • code
  • 98.23 %
  • assert
  • 94.49 %
  • func
  • 86.96 %
  • line
  • 98.93 %
  • branch
  • 98.65 %
  • cond
  • 94.72 %
  • toggle
  • 98.87 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
85.71%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.990s 69.247us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.920s 51.463us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.960s 76.059us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 8.020s 1903.728us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.290s 166.357us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.660s 45.657us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.960s 76.059us 1 1 100.00
clkmgr_csr_aliasing 1.290s 166.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.700s 13.372us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.840s 27.768us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.920s 90.393us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.870s 148.830us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.990s 69.247us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 6.300s 2726.876us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 3.820s 737.556us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 6.300s 2726.876us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 12.700s 4998.397us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.850s 19.328us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.970s 243.544us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.970s 243.544us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.920s 51.463us 1 1 100.00
clkmgr_csr_rw 0.960s 76.059us 1 1 100.00
clkmgr_csr_aliasing 1.290s 166.357us 1 1 100.00
clkmgr_same_csr_outstanding 2.710s 802.327us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.920s 51.463us 1 1 100.00
clkmgr_csr_rw 0.960s 76.059us 1 1 100.00
clkmgr_csr_aliasing 1.290s 166.357us 1 1 100.00
clkmgr_same_csr_outstanding 2.710s 802.327us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_tl_intg_err 3.890s 1288.434us 1 1 100.00
clkmgr_sec_cm 0.830s 20.765us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.950s 230.682us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.950s 230.682us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.950s 230.682us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.950s 230.682us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 3.560s 712.130us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 3.890s 1288.434us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 6.300s 2726.876us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 3.820s 737.556us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.950s 230.682us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.840s 38.544us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.030s 120.191us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.800s 21.518us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.920s 30.862us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.960s 16.802us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.960s 76.059us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.830s 20.765us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.960s 76.059us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.960s 76.059us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.830s 20.765us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 4.110s 1408.880us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 41.900s 6771.048us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 98967753587210006896173226909747534417955232246046262452643792103192237165083 94
UVM_ERROR @ 20765000 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 20765000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---