| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| edn_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| edn_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| edn_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| edn_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 0 | 1 | 0.00 | |||
| edn_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| default | None | None |
INFO: Mapped lowrisc:prim:flop:0 to lowrisc:prim_generic:flop:0.
INFO: Mapped lowrisc:prim:clock_inv:0 to lowrisc:prim_generic:clock_inv:0.
INFO: Mapped lowrisc:prim:clock_buf:0 to lowrisc:prim_generic:clock_buf:0.
INFO: Mapped lowrisc:prim:clock_gating:0 to lowrisc:prim_generic:clock_gating:0.
INFO: Mapped lowrisc:prim:flop_en:0 to lowrisc:prim_generic:flop_en:0.
INFO: Mapped lowrisc:prim:ram_1r1w:0 to lowrisc:prim_generic:ram_1r1w:0.
INFO: Mapped lowrisc:prim:ram_1p:0 to lowrisc:prim_generic:ram_1p:0.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
INFO: Mapped lowrisc:prim:flop_2sync:0 to lowrisc:prim_generic:flop_2sync:0.
INFO: Mapped lowrisc:prim:and2:0 to lowrisc:prim_generic:and2:0.
|
|
| cover_reg_top | None | None |
INFO: Mapped lowrisc:prim:pad_attr:0 to lowrisc:prim_generic:pad_attr:0.
INFO: Mapped lowrisc:prim:flop_2sync:0 to lowrisc:prim_generic:flop_2sync:0.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:30: gen_sv_flist] Error 1
INFO: Mapped lowrisc:prim:clock_gating:0 to lowrisc:prim_generic:clock_gating:0.
INFO: Mapped lowrisc:prim:buf:0 to lowrisc:prim_generic:buf:0.
INFO: Mapped lowrisc:prim:clock_buf:0 to lowrisc:prim_generic:clock_buf:0.
INFO: Mapped lowrisc:prim:clock_div:0 to lowrisc:prim_generic:clock_div:0.
INFO: Mapped lowrisc:prim:clock_gating:0 to lowrisc:prim_generic:clock_gating:0.
INFO: Mapped lowrisc:prim:clock_mux2:0 to lowrisc:prim_generic:clock_mux2:0.
INFO: Mapped lowrisc:prim:clock_buf:0 to lowrisc:prim_generic:clock_buf:0.
|
|
| Job killed most likely because its dependent job failed. | ||||
| edn_smoke | 94233287551251181401744962203989488567156710829312067440416974744341074873030 | None | ||
| edn_regwen | 14794499738114305852089792285240005889094354736589660235176723469697150240054 | None | ||
| edn_genbits | 57766728512779237201392172148310502660797834218517327853539038017563411532543 | None | ||
| edn_stress_all | 48269138949423739776812020193968747233429480253755406570369910748673000584857 | None | ||
| edn_stress_all_with_rand_reset | 78302834818020701644996887273138962777245932616950995930399969796951820201198 | None | ||
| edn_intr | 20865937002598770567610497918381241536566555484475732288663194599341892557453 | None | ||
| edn_alert | 100491714240879586639712736046594643701749832560746160326170238957033590930140 | None | ||
| edn_err | 66203747929987292502460251526205108230104634516733239091974421228910564487991 | None | ||
| edn_disable | 65521773308085699148381988305558157545154247995014529112010064177307896008786 | None | ||
| edn_disable_auto_req_mode | 49529427387070627931641822336733865372637754458653067906833898695939974764427 | None | ||
| edn_sec_cm | 63241572776978854977996976646591102058964235535199737426381150210222046029942 | None | ||
| edn_alert_test | 10137592481520053860787258398226751127060600110128855079118788882810716410382 | None | ||
| edn_tl_errors | 5104252634723532030978083695944595151870316298844523058824948537067744137949 | None | ||
| edn_tl_intg_err | 72551774777886749250319497179501209440916879514212867547295708126977047483489 | None | ||
| edn_intr_test | 22979462520093542384310150361230884231309725797816693412231764495084205258674 | None | ||
| edn_csr_hw_reset | 79581661085456373190202264312516328657943890311545899778703162827638617326101 | None | ||
| edn_csr_rw | 113023656259604248045824543117220665829103995460966372924841076604973046490969 | None | ||
| edn_csr_bit_bash | 37892366364444966988092970893740486147179492899139289878134312332508350858515 | None | ||
| edn_csr_aliasing | 25209149249119612731971006035267012453729162810737889010867743958804624673250 | None | ||
| edn_same_csr_outstanding | 46648904522163542603532065801415494982474553703171829198584851977396378630881 | None | ||
| edn_csr_mem_rw_with_rand_reset | 46375697742832093484276305990140434440448707131831898912660360135081371597767 | None | ||
| edn | None | None | ||
| edn | None | None | ||