Simulation Results: edn

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.01 %
  • code
  • 83.65 %
  • assert
  • 97.14 %
  • func
  • 80.25 %
  • line
  • 97.95 %
  • branch
  • 92.86 %
  • cond
  • 89.46 %
  • toggle
  • 94.80 %
  • FSM
  • 43.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.930s 46.485us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.930s 144.914us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 60.174us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.540s 40.688us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.080s 94.594us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.090s 53.896us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 60.174us 1 1 100.00
edn_csr_aliasing 1.080s 94.594us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.260s 311.145us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.260s 311.145us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.260s 311.145us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.900s 29.173us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.920s 65.724us 1 1 100.00
errs 1 1 100.00
edn_err 1.100s 30.152us 1 1 100.00
disable 2 2 100.00
edn_disable 0.880s 14.795us 1 1 100.00
edn_disable_auto_req_mode 1.110s 54.061us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.700s 2138.701us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.790s 14.361us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.750s 136.437us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.530s 97.291us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.530s 97.291us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.930s 144.914us 1 1 100.00
edn_csr_rw 0.770s 60.174us 1 1 100.00
edn_csr_aliasing 1.080s 94.594us 1 1 100.00
edn_same_csr_outstanding 0.880s 53.468us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.930s 144.914us 1 1 100.00
edn_csr_rw 0.770s 60.174us 1 1 100.00
edn_csr_aliasing 1.080s 94.594us 1 1 100.00
edn_same_csr_outstanding 0.880s 53.468us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.360s 180.575us 1 1 100.00
edn_tl_intg_err 3.340s 264.101us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.810s 16.753us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.920s 65.724us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.360s 180.575us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.360s 180.575us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.360s 180.575us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.360s 180.575us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.920s 65.724us 1 1 100.00
edn_sec_cm 2.360s 180.575us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.920s 65.724us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.340s 264.101us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 50.970s 39256.650us 1 1 100.00

Error Messages

   Test seed line log context