| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke | 69.120s | 140.192us | 1 | 1 | 100.00 | |
| smoke_hw | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke_hw | 10.550s | 107.733us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 13.200s | 251.923us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 8.280s | 28.779us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_bit_bash | 20.280s | 339.354us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_aliasing | 42.090s | 6817.087us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_mem_rw_with_rand_reset | 7.610s | 220.655us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| flash_ctrl_csr_rw | 8.280s | 28.779us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 42.090s | 6817.087us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| flash_ctrl_mem_walk | 5.350s | 39.513us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| flash_ctrl_mem_partial_access | 5.570s | 23.049us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sw_op | 1 | 1 | 100.00 | |||
| flash_ctrl_sw_op | 10.710s | 64.677us | 1 | 1 | 100.00 | |
| host_read_direct | 1 | 1 | 100.00 | |||
| flash_ctrl_host_dir_rd | 39.280s | 297.632us | 1 | 1 | 100.00 | |
| rma_hw_if | 3 | 3 | 100.00 | |||
| flash_ctrl_hw_rma | 1290.220s | 213143.169us | 1 | 1 | 100.00 | |
| flash_ctrl_hw_rma_reset | 559.340s | 270256.618us | 1 | 1 | 100.00 | |
| flash_ctrl_lcmgr_intg | 5.270s | 23.649us | 1 | 1 | 100.00 | |
| host_controller_arb | 1 | 1 | 100.00 | |||
| flash_ctrl_host_ctrl_arb | 1235.140s | 381969.987us | 1 | 1 | 100.00 | |
| erase_suspend | 1 | 1 | 100.00 | |||
| flash_ctrl_erase_suspend | 164.080s | 1447.485us | 1 | 1 | 100.00 | |
| program_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_prog_reset | 112.800s | 1966.196us | 1 | 1 | 100.00 | |
| full_memory_access | 1 | 1 | 100.00 | |||
| flash_ctrl_full_mem_access | 1507.350s | 365127.782us | 1 | 1 | 100.00 | |
| rd_buff_eviction | 1 | 1 | 100.00 | |||
| flash_ctrl_rd_buff_evict | 74.420s | 2590.707us | 1 | 1 | 100.00 | |
| rd_buff_eviction_w_ecc | 3 | 3 | 100.00 | |||
| flash_ctrl_rw_evict | 16.950s | 31.842us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_evict_all_en | 16.970s | 28.259us | 1 | 1 | 100.00 | |
| flash_ctrl_re_evict | 19.260s | 197.406us | 1 | 1 | 100.00 | |
| host_arb | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb | 145.270s | 1144.060us | 1 | 1 | 100.00 | |
| host_interleave | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb | 145.270s | 1144.060us | 1 | 1 | 100.00 | |
| memory_protection | 1 | 1 | 100.00 | |||
| flash_ctrl_mp_regions | 292.180s | 52736.810us | 1 | 1 | 100.00 | |
| fetch_code | 1 | 1 | 100.00 | |||
| flash_ctrl_fetch_code | 18.870s | 493.394us | 1 | 1 | 100.00 | |
| all_partitions | 1 | 1 | 100.00 | |||
| flash_ctrl_rand_ops | 22.070s | 122.885us | 1 | 1 | 100.00 | |
| error_mp | 1 | 1 | 100.00 | |||
| flash_ctrl_error_mp | 351.810s | 25549.923us | 1 | 1 | 100.00 | |
| error_prog_win | 1 | 1 | 100.00 | |||
| flash_ctrl_error_prog_win | 299.460s | 2853.491us | 1 | 1 | 100.00 | |
| error_prog_type | 1 | 1 | 100.00 | |||
| flash_ctrl_error_prog_type | 657.530s | 756.627us | 1 | 1 | 100.00 | |
| error_read_seed | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_read_seed_err | 5.220s | 61.942us | 1 | 1 | 100.00 | |
| read_write_overflow | 1 | 1 | 100.00 | |||
| flash_ctrl_oversize_error | 94.870s | 3224.289us | 1 | 1 | 100.00 | |
| flash_ctrl_disable | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 12.010s | 62.902us | 1 | 1 | 100.00 | |
| flash_ctrl_connect | 1 | 1 | 100.00 | |||
| flash_ctrl_connect | 6.510s | 17.328us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| flash_ctrl_stress_all | 443.990s | 1517.961us | 1 | 1 | 100.00 | |
| secret_partition | 2 | 2 | 100.00 | |||
| flash_ctrl_hw_sec_otp | 51.000s | 8691.772us | 1 | 1 | 100.00 | |
| flash_ctrl_otp_reset | 54.360s | 83.546us | 1 | 1 | 100.00 | |
| isolation_partition | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_rma | 1290.220s | 213143.169us | 1 | 1 | 100.00 | |
| interrupts | 4 | 4 | 100.00 | |||
| flash_ctrl_intr_rd | 82.840s | 1921.130us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_wr | 63.630s | 28199.131us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_rd_slow_flash | 85.390s | 13037.434us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_wr_slow_flash | 145.840s | 67463.277us | 1 | 1 | 100.00 | |
| invalid_op | 1 | 1 | 100.00 | |||
| flash_ctrl_invalid_op | 48.640s | 847.138us | 1 | 1 | 100.00 | |
| mid_op_rst | 1 | 1 | 100.00 | |||
| flash_ctrl_mid_op_rst | 39.440s | 864.089us | 1 | 1 | 100.00 | |
| double_bit_err | 5 | 5 | 100.00 | |||
| flash_ctrl_read_word_sweep_derr | 10.350s | 293.385us | 1 | 1 | 100.00 | |
| flash_ctrl_ro_derr | 95.960s | 613.834us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_derr | 155.480s | 11112.075us | 1 | 1 | 100.00 | |
| flash_ctrl_derr_detect | 93.190s | 1651.996us | 1 | 1 | 100.00 | |
| flash_ctrl_integrity | 362.450s | 38574.004us | 1 | 1 | 100.00 | |
| single_bit_err | 3 | 3 | 100.00 | |||
| flash_ctrl_read_word_sweep_serr | 11.020s | 26.958us | 1 | 1 | 100.00 | |
| flash_ctrl_ro_serr | 78.700s | 1187.675us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_serr | 120.720s | 7590.354us | 1 | 1 | 100.00 | |
| singlebit_err_counter | 1 | 1 | 100.00 | |||
| flash_ctrl_serr_counter | 53.880s | 920.033us | 1 | 1 | 100.00 | |
| singlebit_err_address | 1 | 1 | 100.00 | |||
| flash_ctrl_serr_address | 39.910s | 1466.855us | 1 | 1 | 100.00 | |
| scramble | 5 | 5 | 100.00 | |||
| flash_ctrl_wo | 110.380s | 15597.128us | 1 | 1 | 100.00 | |
| flash_ctrl_write_word_sweep | 8.440s | 195.591us | 1 | 1 | 100.00 | |
| flash_ctrl_read_word_sweep | 10.410s | 148.685us | 1 | 1 | 100.00 | |
| flash_ctrl_ro | 71.570s | 568.917us | 1 | 1 | 100.00 | |
| flash_ctrl_rw | 327.960s | 3875.299us | 1 | 1 | 100.00 | |
| filesystem_support | 1 | 1 | 100.00 | |||
| flash_ctrl_fs_sup | 21.400s | 1183.902us | 1 | 1 | 100.00 | |
| rma_write_process_error | 2 | 2 | 100.00 | |||
| flash_ctrl_rma_err | 689.960s | 358486.958us | 1 | 1 | 100.00 | |
| flash_ctrl_hw_prog_rma_wipe_err | 78.590s | 10020.156us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| flash_ctrl_alert_test | 5.730s | 64.085us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| flash_ctrl_intr_test | 7.460s | 18.524us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_errors | 8.160s | 136.246us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_errors | 8.160s | 136.246us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 13.200s | 251.923us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_rw | 8.280s | 28.779us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 42.090s | 6817.087us | 1 | 1 | 100.00 | |
| flash_ctrl_same_csr_outstanding | 10.330s | 80.435us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 13.200s | 251.923us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_rw | 8.280s | 28.779us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 42.090s | 6817.087us | 1 | 1 | 100.00 | |
| flash_ctrl_same_csr_outstanding | 10.330s | 80.435us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 35.680s | 117.512us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 35.680s | 117.512us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 35.680s | 117.512us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 35.680s | 117.512us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors_with_csr_rw | 9.550s | 134.382us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| flash_ctrl_tl_intg_err | 182.490s | 1767.344us | 1 | 1 | 100.00 | |
| flash_ctrl_sec_cm | 1448.110s | 5140.601us | 1 | 1 | 100.00 | |
| sec_cm_reg_bus_integrity | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_intg_err | 182.490s | 1767.344us | 1 | 1 | 100.00 | |
| sec_cm_host_bus_integrity | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_intg_err | 182.490s | 1767.344us | 1 | 1 | 100.00 | |
| sec_cm_mem_bus_integrity | 2 | 2 | 100.00 | |||
| flash_ctrl_rd_intg | 13.730s | 69.056us | 1 | 1 | 100.00 | |
| flash_ctrl_wr_intg | 6.900s | 57.425us | 1 | 1 | 100.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke | 69.120s | 140.192us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 4 | 4 | 100.00 | |||
| flash_ctrl_otp_reset | 54.360s | 83.546us | 1 | 1 | 100.00 | |
| flash_ctrl_disable | 12.010s | 62.902us | 1 | 1 | 100.00 | |
| flash_ctrl_sec_info_access | 37.070s | 966.044us | 1 | 1 | 100.00 | |
| flash_ctrl_connect | 6.510s | 17.328us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_config_regwen | 7.040s | 26.927us | 1 | 1 | 100.00 | |
| sec_cm_data_regions_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 8.280s | 28.779us | 1 | 1 | 100.00 | |
| sec_cm_data_regions_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 35.680s | 117.512us | 1 | 1 | 100.00 | |
| sec_cm_info_regions_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 8.280s | 28.779us | 1 | 1 | 100.00 | |
| sec_cm_info_regions_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 35.680s | 117.512us | 1 | 1 | 100.00 | |
| sec_cm_bank_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 8.280s | 28.779us | 1 | 1 | 100.00 | |
| sec_cm_bank_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 35.680s | 117.512us | 1 | 1 | 100.00 | |
| sec_cm_mem_ctrl_global_esc | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 12.010s | 62.902us | 1 | 1 | 100.00 | |
| sec_cm_mem_ctrl_local_esc | 2 | 2 | 100.00 | |||
| flash_ctrl_rd_intg | 13.730s | 69.056us | 1 | 1 | 100.00 | |
| flash_ctrl_access_after_disable | 5.610s | 76.816us | 1 | 1 | 100.00 | |
| sec_cm_mem_addr_infection | 1 | 1 | 100.00 | |||
| flash_ctrl_host_addr_infection | 12.550s | 27.715us | 1 | 1 | 100.00 | |
| sec_cm_mem_disable_config_mubi | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 12.010s | 62.902us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_fetch_code | 18.870s | 493.394us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| flash_ctrl_rw | 327.960s | 3875.299us | 1 | 1 | 100.00 | |
| sec_cm_mem_integrity | 3 | 3 | 100.00 | |||
| flash_ctrl_rw_serr | 120.720s | 7590.354us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_derr | 155.480s | 11112.075us | 1 | 1 | 100.00 | |
| flash_ctrl_integrity | 362.450s | 38574.004us | 1 | 1 | 100.00 | |
| sec_cm_rma_entry_mem_sec_wipe | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_rma | 1290.220s | 213143.169us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1448.110s | 5140.601us | 1 | 1 | 100.00 | |
| sec_cm_phy_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1448.110s | 5140.601us | 1 | 1 | 100.00 | |
| sec_cm_phy_prog_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1448.110s | 5140.601us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1448.110s | 5140.601us | 1 | 1 | 100.00 | |
| sec_cm_phy_arbiter_ctrl_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb_redun | 9.800s | 948.944us | 1 | 1 | 100.00 | |
| sec_cm_phy_host_grant_ctrl_consistency | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_host_grant_err | 5.670s | 73.862us | 1 | 1 | 100.00 | |
| sec_cm_phy_ack_ctrl_consistency | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_ack_consistency | 7.270s | 116.812us | 1 | 1 | 100.00 | |
| sec_cm_fifo_ctr_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1448.110s | 5140.601us | 1 | 1 | 100.00 | |
| sec_cm_mem_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1448.110s | 5140.601us | 1 | 1 | 100.00 | |
| sec_cm_prog_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1448.110s | 5140.601us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| asymmetric_read_path | 1 | 1 | 100.00 | |||
| flash_ctrl_rd_ooo | 18.920s | 914.893us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| flash_ctrl_basic_rw | 342.760s | 1418.372us | 1 | 1 | 100.00 | |
| Test | seed | line | log context |
|---|