| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 4 | 4 | 100.00 | |||
| gpio_smoke | 1.100s | 286.515us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 1.220s | 226.913us | 1 | 1 | 100.00 | |
| gpio_smoke_en_cdc_prim | 1.200s | 333.896us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 0.940s | 43.882us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 0.780s | 31.526us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| gpio_csr_rw | 0.930s | 33.782us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 2.530s | 2877.553us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 0.650s | 21.652us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.310s | 28.862us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| gpio_csr_rw | 0.930s | 33.782us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 0.650s | 21.652us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 2 | 2 | 100.00 | |||
| gpio_random_dout_din | 1.030s | 38.579us | 1 | 1 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 1.020s | 85.835us | 1 | 1 | 100.00 | |
| out_in_regs_read_write | 1 | 1 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 0.750s | 305.805us | 1 | 1 | 100.00 | |
| gpio_interrupt_programming | 1 | 1 | 100.00 | |||
| gpio_intr_rand_pgm | 0.750s | 40.067us | 1 | 1 | 100.00 | |
| random_interrupt_trigger | 1 | 1 | 100.00 | |||
| gpio_rand_intr_trigger | 1.240s | 54.934us | 1 | 1 | 100.00 | |
| interrupt_and_noise_filter | 1 | 1 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 1.660s | 416.702us | 1 | 1 | 100.00 | |
| noise_filter_stress | 1 | 1 | 100.00 | |||
| gpio_filter_stress | 12.840s | 378.567us | 1 | 1 | 100.00 | |
| regs_long_reads_and_writes | 1 | 1 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 3.690s | 8931.597us | 1 | 1 | 100.00 | |
| full_random | 1 | 1 | 100.00 | |||
| gpio_full_random | 0.850s | 229.465us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| gpio_stress_all | 76.100s | 8344.453us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| gpio_alert_test | 0.670s | 15.340us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| gpio_intr_test | 0.790s | 39.974us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 1.500s | 78.518us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 1.500s | 78.518us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 0.930s | 33.782us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 0.780s | 115.727us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 0.650s | 21.652us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.780s | 31.526us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 0.930s | 33.782us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 0.780s | 115.727us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 0.650s | 21.652us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.780s | 31.526us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| gpio_sec_cm | 0.940s | 63.439us | 1 | 1 | 100.00 | |
| gpio_tl_intg_err | 1.100s | 430.199us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| gpio_tl_intg_err | 1.100s | 430.199us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 1 | 1 | 100.00 | |||
| gpio_rand_straps | 0.790s | 12.593us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 0.720s | 8.051us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (cip_base_vseq.sv:1163) [gpio_common_vseq] Check failed (vseq_done) | ||||
| gpio_stress_all_with_rand_reset | 86251463286640542939548962231823267067211376064722716196032328952275542470925 | 77 |
UVM_FATAL @ 8051320 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 8051320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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