Simulation Results: hmac

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.36 %
  • code
  • 96.68 %
  • assert
  • 96.42 %
  • func
  • 41.98 %
  • line
  • 99.21 %
  • branch
  • 97.85 %
  • cond
  • 95.39 %
  • toggle
  • 99.77 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.190s 125.924us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.040s 153.200us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.960s 289.340us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.490s 729.131us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.640s 246.358us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.290s 148.046us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.960s 289.340us 1 1 100.00
hmac_csr_aliasing 2.640s 246.358us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 12.050s 1731.781us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 20.010s 515.234us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 187.770s 5494.852us 1 1 100.00
hmac_test_sha384_vectors 20.640s 1381.593us 1 1 100.00
hmac_test_sha512_vectors 21.350s 992.827us 1 1 100.00
hmac_test_hmac256_vectors 7.090s 201.219us 1 1 100.00
hmac_test_hmac384_vectors 10.730s 1375.875us 1 1 100.00
hmac_test_hmac512_vectors 10.910s 315.719us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 18.550s 3656.622us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 24.600s 262.820us 1 1 100.00
error 1 1 100.00
hmac_error 47.270s 5233.232us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 66.360s 23203.442us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.190s 125.924us 1 1 100.00
hmac_long_msg 12.050s 1731.781us 1 1 100.00
hmac_back_pressure 20.010s 515.234us 1 1 100.00
hmac_datapath_stress 24.600s 262.820us 1 1 100.00
hmac_burst_wr 18.550s 3656.622us 1 1 100.00
hmac_stress_all 188.660s 273885.537us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.190s 125.924us 1 1 100.00
hmac_long_msg 12.050s 1731.781us 1 1 100.00
hmac_back_pressure 20.010s 515.234us 1 1 100.00
hmac_datapath_stress 24.600s 262.820us 1 1 100.00
hmac_wipe_secret 66.360s 23203.442us 1 1 100.00
hmac_test_sha256_vectors 187.770s 5494.852us 1 1 100.00
hmac_test_sha384_vectors 20.640s 1381.593us 1 1 100.00
hmac_test_sha512_vectors 21.350s 992.827us 1 1 100.00
hmac_test_hmac256_vectors 7.090s 201.219us 1 1 100.00
hmac_test_hmac384_vectors 10.730s 1375.875us 1 1 100.00
hmac_test_hmac512_vectors 10.910s 315.719us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.190s 125.924us 1 1 100.00
hmac_long_msg 12.050s 1731.781us 1 1 100.00
hmac_back_pressure 20.010s 515.234us 1 1 100.00
hmac_datapath_stress 24.600s 262.820us 1 1 100.00
hmac_burst_wr 18.550s 3656.622us 1 1 100.00
hmac_error 47.270s 5233.232us 1 1 100.00
hmac_wipe_secret 66.360s 23203.442us 1 1 100.00
hmac_test_sha256_vectors 187.770s 5494.852us 1 1 100.00
hmac_test_sha384_vectors 20.640s 1381.593us 1 1 100.00
hmac_test_sha512_vectors 21.350s 992.827us 1 1 100.00
hmac_test_hmac256_vectors 7.090s 201.219us 1 1 100.00
hmac_test_hmac384_vectors 10.730s 1375.875us 1 1 100.00
hmac_test_hmac512_vectors 10.910s 315.719us 1 1 100.00
hmac_stress_all 188.660s 273885.537us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 188.660s 273885.537us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.830s 48.907us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.690s 76.560us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.700s 382.323us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.700s 382.323us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.040s 153.200us 1 1 100.00
hmac_csr_rw 0.960s 289.340us 1 1 100.00
hmac_csr_aliasing 2.640s 246.358us 1 1 100.00
hmac_same_csr_outstanding 1.160s 91.269us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.040s 153.200us 1 1 100.00
hmac_csr_rw 0.960s 289.340us 1 1 100.00
hmac_csr_aliasing 2.640s 246.358us 1 1 100.00
hmac_same_csr_outstanding 1.160s 91.269us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 2.420s 95.897us 1 1 100.00
hmac_sec_cm 0.980s 261.798us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.420s 95.897us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.190s 125.924us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 0.920s 28.764us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 56.530s 5067.481us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.170s 90.507us 1 1 100.00

Error Messages

   Test seed line log context