Simulation Results: i2c

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.74 %
  • code
  • 81.84 %
  • assert
  • 96.19 %
  • func
  • 79.18 %
  • line
  • 96.75 %
  • branch
  • 92.69 %
  • cond
  • 84.86 %
  • toggle
  • 89.66 %
  • FSM
  • 45.24 %
Validation stages
V1
100.00%
V2
85.71%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 44.710s 1467.403us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 24.380s 4617.327us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.860s 27.358us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.820s 23.326us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.290s 1331.926us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.720s 111.472us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.020s 151.084us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.820s 23.326us 1 1 100.00
i2c_csr_aliasing 1.720s 111.472us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.980s 303.897us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 571.840s 22220.625us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 86.500s 13252.978us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.800s 46.122us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 97.960s 4876.084us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 36.350s 4189.956us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.270s 397.832us 1 1 100.00
i2c_host_fifo_fmt_empty 11.160s 2004.980us 1 1 100.00
i2c_host_fifo_reset_rx 3.870s 572.664us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 114.470s 5872.590us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 19.910s 1286.458us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 0.890s 24.970us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 2.010s 1206.949us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 54.100s 48267.115us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.730s 654.138us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 8.610s 699.698us 1 1 100.00
i2c_target_intr_smoke 4.880s 5541.899us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.860s 279.550us 1 1 100.00
i2c_target_fifo_reset_tx 1.600s 580.944us 1 1 100.00
target_fifo_full 2 3 66.67
i2c_target_stress_wr 213.180s 53197.002us 1 1 100.00
i2c_target_stress_rd 8.610s 699.698us 1 1 100.00
i2c_target_intr_stress_wr 93.800s 47991.136us 0 1 0.00
target_timeout 1 1 100.00
i2c_target_timeout 5.390s 10356.118us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 39.980s 4152.687us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.170s 1922.070us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 3.570s 11303.223us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.140s 1918.003us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.410s 315.648us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 86.500s 13252.978us 1 1 100.00
i2c_host_perf_precise 1.180s 60.320us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 19.910s 1286.458us 1 1 100.00
target_mode_tx_stretch_ctrl 0 1 0.00
i2c_target_tx_stretch_ctrl 0.880s 2.444us 0 1 0.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 2.260s 4230.746us 1 1 100.00
i2c_target_nack_acqfull_addr 1.980s 1946.486us 1 1 100.00
i2c_target_nack_txstretch 1.390s 144.582us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 4.610s 461.404us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.840s 1774.333us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.740s 46.384us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.860s 26.616us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.590s 43.801us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.590s 43.801us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.860s 27.358us 1 1 100.00
i2c_csr_rw 0.820s 23.326us 1 1 100.00
i2c_csr_aliasing 1.720s 111.472us 1 1 100.00
i2c_same_csr_outstanding 0.810s 127.962us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.860s 27.358us 1 1 100.00
i2c_csr_rw 0.820s 23.326us 1 1 100.00
i2c_csr_aliasing 1.720s 111.472us 1 1 100.00
i2c_same_csr_outstanding 0.810s 127.962us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.550s 82.976us 1 1 100.00
i2c_sec_cm 1.310s 102.348us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.550s 82.976us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 41.430s 1821.375us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.050s 35.266us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 6.270s 2057.368us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 72242059214586969810244444754601256852140887098663602086431724727948823696912 99
UVM_ERROR @ 303896589 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 303896589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_mode_toggle 52462690670580793548393135380911883453432971937485911509758917256960024373859 78
UVM_ERROR @ 24969701 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 24969701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
i2c_host_stress_all 10067260840603330936010541369353832279078608560977572944422664930933414696473 211
UVM_ERROR @ 22220625257 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3859993
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 65678073324072367681728622949026319961541622146903496862968327319843878333704 81
UVM_ERROR @ 1206949491 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 1206949491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
i2c_target_intr_stress_wr 2697969656356681479972335959673559912085578036849253770894454537807238866871 75
UVM_FATAL @ 47991135680 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 47991135680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 33114147278815410564039527538619196799132752354330025124271856443764851991649 75
UVM_ERROR @ 35265791 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 172 [0xac])
UVM_INFO @ 35265791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 40556549759198573161468549556235495289489741407394460620059359129249032077128 76
UVM_FATAL @ 11303222904 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 11303222904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 80125120099442784443172988904012577852208705603543071498728688503380384436705 91
UVM_ERROR @ 1821374524 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1821374524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 28164573188238293027296995439487081529618313695257065710919134228198175840152 82
UVM_ERROR @ 2057367775 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2057367775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure
i2c_target_tx_stretch_ctrl 51048895541625857318896187966326206504078638514003091757588453027243216069381 121
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.