Simulation Results: keymgr

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.37 %
  • code
  • 95.05 %
  • assert
  • 97.49 %
  • func
  • 63.58 %
  • line
  • 98.74 %
  • branch
  • 97.67 %
  • cond
  • 93.09 %
  • toggle
  • 97.39 %
  • FSM
  • 88.37 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 1.990s 784.985us 1 1 100.00
random 1 1 100.00
keymgr_random 2.430s 282.285us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.100s 101.727us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.000s 54.312us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 8.130s 253.533us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 3.200s 67.818us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.140s 88.203us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.000s 54.312us 1 1 100.00
keymgr_csr_aliasing 3.200s 67.818us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 3.460s 89.170us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.000s 131.612us 1 1 100.00
keymgr_sideload_kmac 1.730s 65.563us 1 1 100.00
keymgr_sideload_aes 1.790s 349.764us 1 1 100.00
keymgr_sideload_otbn 1.850s 46.461us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.250s 145.467us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 3.750s 568.104us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.530s 217.621us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 4.860s 248.313us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 1.550s 60.752us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 3.390s 527.639us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 21.270s 906.193us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.740s 38.750us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.640s 88.841us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.200s 179.477us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.200s 179.477us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.100s 101.727us 1 1 100.00
keymgr_csr_rw 1.000s 54.312us 1 1 100.00
keymgr_csr_aliasing 3.200s 67.818us 1 1 100.00
keymgr_same_csr_outstanding 1.990s 113.255us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.100s 101.727us 1 1 100.00
keymgr_csr_rw 1.000s 54.312us 1 1 100.00
keymgr_csr_aliasing 3.200s 67.818us 1 1 100.00
keymgr_same_csr_outstanding 1.990s 113.255us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 9.330s 640.436us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 9.330s 640.436us 1 1 100.00
keymgr_tl_intg_err 3.820s 505.452us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.490s 323.250us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.490s 323.250us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.490s 323.250us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.490s 323.250us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 4.080s 452.350us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 9.330s 640.436us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 9.330s 640.436us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 3.820s 505.452us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.490s 323.250us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 3.460s 89.170us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 2.430s 282.285us 1 1 100.00
keymgr_csr_rw 1.000s 54.312us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 2.430s 282.285us 1 1 100.00
keymgr_csr_rw 1.000s 54.312us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 2.430s 282.285us 1 1 100.00
keymgr_csr_rw 1.000s 54.312us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 3.750s 568.104us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.550s 60.752us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.550s 60.752us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 2.430s 282.285us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.670s 74.522us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 9.330s 640.436us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 9.330s 640.436us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 9.330s 640.436us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.950s 352.553us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 3.750s 568.104us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 9.330s 640.436us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 9.330s 640.436us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 9.330s 640.436us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.950s 352.553us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.950s 352.553us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 9.330s 640.436us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.950s 352.553us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 9.330s 640.436us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.950s 352.553us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
keymgr_stress_all_with_rand_reset 15.250s 378.953us 1 1 100.00

Error Messages

   Test seed line log context