| V1 |
|
100.00% |
| V2 |
|
87.50% |
| V2S |
|
67.86% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| lc_ctrl_smoke | 2.750s | 471.497us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_hw_reset | 0.980s | 41.487us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_rw | 1.080s | 12.230us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_bit_bash | 1.590s | 213.538us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_aliasing | 1.070s | 50.167us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| lc_ctrl_csr_mem_rw_with_rand_reset | 1.000s | 19.797us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| lc_ctrl_csr_rw | 1.080s | 12.230us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 1.070s | 50.167us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| state_post_trans | 0 | 1 | 0.00 | |||
| lc_ctrl_state_post_trans | 3.920s | 171.881us | 0 | 1 | 0.00 | |
| regwen_during_op | 1 | 1 | 100.00 | |||
| lc_ctrl_regwen_during_op | 4.270s | 1180.571us | 1 | 1 | 100.00 | |
| rand_wr_claim_transition_if | 1 | 1 | 100.00 | |||
| lc_ctrl_claim_transition_if | 0.810s | 13.549us | 1 | 1 | 100.00 | |
| lc_prog_failure | 1 | 1 | 100.00 | |||
| lc_ctrl_prog_failure | 1.980s | 296.680us | 1 | 1 | 100.00 | |
| lc_state_failure | 0 | 1 | 0.00 | |||
| lc_ctrl_state_failure | 4.930s | 96.783us | 0 | 1 | 0.00 | |
| lc_errors | 1 | 1 | 100.00 | |||
| lc_ctrl_errors | 6.410s | 320.449us | 1 | 1 | 100.00 | |
| security_escalation | 5 | 7 | 71.43 | |||
| lc_ctrl_state_failure | 4.930s | 96.783us | 0 | 1 | 0.00 | |
| lc_ctrl_prog_failure | 1.980s | 296.680us | 1 | 1 | 100.00 | |
| lc_ctrl_errors | 6.410s | 320.449us | 1 | 1 | 100.00 | |
| lc_ctrl_security_escalation | 5.920s | 404.602us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_state_failure | 1.720s | 65.440us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_prog_failure | 16.410s | 3835.080us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_errors | 44.650s | 10071.080us | 1 | 1 | 100.00 | |
| jtag_access | 13 | 13 | 100.00 | |||
| lc_ctrl_jtag_csr_hw_reset | 1.680s | 393.862us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_rw | 1.370s | 44.164us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_bit_bash | 7.050s | 1499.417us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_aliasing | 3.220s | 2176.410us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_same_csr_outstanding | 1.500s | 155.404us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 4.040s | 290.335us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_alert_test | 1.200s | 235.927us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_smoke | 4.550s | 1720.170us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_state_post_trans | 11.390s | 570.789us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_prog_failure | 16.410s | 3835.080us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_errors | 44.650s | 10071.080us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_access | 3.640s | 433.054us | 1 | 1 | 100.00 | |
| lc_ctrl_jtag_regwen_during_op | 11.890s | 10531.094us | 1 | 1 | 100.00 | |
| jtag_priority | 1 | 1 | 100.00 | |||
| lc_ctrl_jtag_priority | 2.480s | 579.638us | 1 | 1 | 100.00 | |
| lc_ctrl_volatile_unlock | 1 | 1 | 100.00 | |||
| lc_ctrl_volatile_unlock_smoke | 0.860s | 22.858us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| lc_ctrl_stress_all | 67.510s | 20382.571us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| lc_ctrl_alert_test | 1.040s | 20.444us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_errors | 3.710s | 293.175us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_errors | 3.710s | 293.175us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| lc_ctrl_csr_hw_reset | 0.980s | 41.487us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_rw | 1.080s | 12.230us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 1.070s | 50.167us | 1 | 1 | 100.00 | |
| lc_ctrl_same_csr_outstanding | 0.920s | 29.233us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| lc_ctrl_csr_hw_reset | 0.980s | 41.487us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_rw | 1.080s | 12.230us | 1 | 1 | 100.00 | |
| lc_ctrl_csr_aliasing | 1.070s | 50.167us | 1 | 1 | 100.00 | |
| lc_ctrl_same_csr_outstanding | 0.920s | 29.233us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| lc_ctrl_tl_intg_err | 1.870s | 288.110us | 1 | 1 | 100.00 | |
| lc_ctrl_sec_cm | 7.300s | 454.425us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| lc_ctrl_tl_intg_err | 1.870s | 288.110us | 1 | 1 | 100.00 | |
| sec_cm_transition_config_regwen | 1 | 1 | 100.00 | |||
| lc_ctrl_regwen_during_op | 4.270s | 1180.571us | 1 | 1 | 100.00 | |
| sec_cm_manuf_state_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 4.930s | 96.783us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 7.300s | 454.425us | 1 | 1 | 100.00 | |
| sec_cm_transition_ctr_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 4.930s | 96.783us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 7.300s | 454.425us | 1 | 1 | 100.00 | |
| sec_cm_manuf_state_bkgn_chk | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 4.930s | 96.783us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 7.300s | 454.425us | 1 | 1 | 100.00 | |
| sec_cm_transition_ctr_bkgn_chk | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 4.930s | 96.783us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 7.300s | 454.425us | 1 | 1 | 100.00 | |
| sec_cm_state_config_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 4.930s | 96.783us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 7.300s | 454.425us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 4.930s | 96.783us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 7.300s | 454.425us | 1 | 1 | 100.00 | |
| sec_cm_kmac_fsm_sparse | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 4.930s | 96.783us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 7.300s | 454.425us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_local_esc | 1 | 2 | 50.00 | |||
| lc_ctrl_state_failure | 4.930s | 96.783us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 7.300s | 454.425us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_global_esc | 1 | 1 | 100.00 | |||
| lc_ctrl_security_escalation | 5.920s | 404.602us | 1 | 1 | 100.00 | |
| sec_cm_main_ctrl_flow_consistency | 1 | 2 | 50.00 | |||
| lc_ctrl_state_post_trans | 3.920s | 171.881us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_state_post_trans | 11.390s | 570.789us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_mubi | 16.240s | 1143.833us | 1 | 1 | 100.00 | |
| sec_cm_token_valid_ctrl_mubi | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_mubi | 16.240s | 1143.833us | 1 | 1 | 100.00 | |
| sec_cm_token_digest | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_digest | 8.210s | 680.495us | 1 | 1 | 100.00 | |
| sec_cm_token_mux_ctrl_redun | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_mux | 4.460s | 1357.205us | 1 | 1 | 100.00 | |
| sec_cm_token_valid_mux_redun | 1 | 1 | 100.00 | |||
| lc_ctrl_sec_token_mux | 4.460s | 1357.205us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| lc_ctrl_stress_all_with_rand_reset | 17.550s | 13108.716us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' | ||||
| lc_ctrl_state_failure | 79186313221888840863743959029131441093687247490195583072014842091930217180543 | 638 |
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 96783030 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 96783030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| lc_ctrl_state_post_trans | 34987868876158478895176150174631424465619434359528357487681958506865502511041 | 626 |
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 171881114 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 171881114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| lc_ctrl_jtag_state_failure | 66643404112215669498248187638390883960581587743357708614723746552681507757157 | 194 |
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 65440316 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 65440316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| lc_ctrl_stress_all | 66995159854435883246148263016947451596191950106465505319804830484903392280909 | 4669 |
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 20382571263 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 20382571263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| lc_ctrl_stress_all_with_rand_reset | 50324014750190903975203179936540655955542956254574463555280024281881919784095 | 1451 |
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 13108716072 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 13108716072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|