Simulation Results: lc_ctrl

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.43 %
  • code
  • 82.38 %
  • assert
  • 94.13 %
  • func
  • 88.79 %
  • line
  • 96.97 %
  • branch
  • 93.18 %
  • cond
  • 78.66 %
  • toggle
  • 73.63 %
  • FSM
  • 69.47 %
Validation stages
V1
100.00%
V2
87.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.410s 47.964us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.870s 13.886us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.220s 19.303us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.190s 68.254us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 45.795us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.050s 29.894us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.220s 19.303us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 45.795us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.230s 52.358us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.430s 374.589us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.700s 20.532us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.130s 315.558us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 4.950s 50.225us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.250s 263.413us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 4.950s 50.225us 0 1 0.00
lc_ctrl_prog_failure 2.130s 315.558us 1 1 100.00
lc_ctrl_errors 5.250s 263.413us 1 1 100.00
lc_ctrl_security_escalation 4.610s 1257.598us 1 1 100.00
lc_ctrl_jtag_state_failure 2.110s 1800.393us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.860s 385.273us 1 1 100.00
lc_ctrl_jtag_errors 38.950s 39274.644us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 1.140s 222.152us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.020s 134.882us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.220s 2184.530us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.950s 567.486us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.590s 141.046us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.640s 427.798us 1 1 100.00
lc_ctrl_jtag_alert_test 1.530s 240.234us 1 1 100.00
lc_ctrl_jtag_smoke 1.880s 505.623us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.390s 333.319us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.860s 385.273us 1 1 100.00
lc_ctrl_jtag_errors 38.950s 39274.644us 1 1 100.00
lc_ctrl_jtag_access 10.280s 4366.385us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 29.100s 2589.587us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.680s 361.727us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.770s 41.757us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 238.340s 50766.650us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.010s 18.437us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.600s 289.246us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.600s 289.246us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.870s 13.886us 1 1 100.00
lc_ctrl_csr_rw 1.220s 19.303us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 45.795us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.450s 43.623us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.870s 13.886us 1 1 100.00
lc_ctrl_csr_rw 1.220s 19.303us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 45.795us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.450s 43.623us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 3.130s 260.440us 1 1 100.00
lc_ctrl_sec_cm 5.250s 160.496us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.130s 260.440us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.430s 374.589us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 4.950s 50.225us 0 1 0.00
lc_ctrl_sec_cm 5.250s 160.496us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 4.950s 50.225us 0 1 0.00
lc_ctrl_sec_cm 5.250s 160.496us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.950s 50.225us 0 1 0.00
lc_ctrl_sec_cm 5.250s 160.496us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.950s 50.225us 0 1 0.00
lc_ctrl_sec_cm 5.250s 160.496us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 4.950s 50.225us 0 1 0.00
lc_ctrl_sec_cm 5.250s 160.496us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.950s 50.225us 0 1 0.00
lc_ctrl_sec_cm 5.250s 160.496us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.950s 50.225us 0 1 0.00
lc_ctrl_sec_cm 5.250s 160.496us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 4.950s 50.225us 0 1 0.00
lc_ctrl_sec_cm 5.250s 160.496us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.610s 1257.598us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 1.230s 52.358us 0 1 0.00
lc_ctrl_jtag_state_post_trans 9.390s 333.319us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.480s 1093.890us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.480s 1093.890us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.360s 273.093us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.270s 1473.143us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.270s 1473.143us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 8.510s 821.527us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 12723176229137317676643622210312692835287292568214746233208339443652600482431 768
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 50225324 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 50225324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_state_post_trans 68273878321926959825379660092865940978864495005371367125616331091858629439488 170
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 52358406 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 52358406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 102910752530040084634627913301868559472249884675326195448254551619524447699784 429
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1800393311 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1800393311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 70585001950781574213863479815553975205814397295990280411112046619995945085139 14907
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 50766650122 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 50766650122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 10225656733736650352296487813371354712314150320966096847403184997991649847296 805
UVM_ERROR @ 821527121 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 821527121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---