Simulation Results: otp_ctrl

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.96 %
  • code
  • 77.01 %
  • assert
  • 93.65 %
  • func
  • 66.21 %
  • line
  • 88.24 %
  • branch
  • 83.07 %
  • cond
  • 89.69 %
  • toggle
  • 83.24 %
  • FSM
  • 40.80 %
Validation stages
V1
90.91%
V2
92.00%
V2S
96.43%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.580s 54.897us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 6.630s 430.253us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.640s 136.792us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.420s 42.915us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 6.470s 431.277us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.590s 243.549us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.120s 77.662us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.420s 42.915us 1 1 100.00
otp_ctrl_csr_aliasing 3.590s 243.549us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.650s 111.178us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.240s 153.137us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.760s 929.190us 1 1 100.00
init_fail 0 1 0.00
otp_ctrl_init_fail 2.810s 380.432us 0 1 0.00
partition_check 1 2 50.00
otp_ctrl_background_chks 7.120s 384.323us 1 1 100.00
otp_ctrl_check_fail 8.780s 513.185us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 6.780s 539.088us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 10.500s 1335.240us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 14.760s 915.377us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 11.300s 483.541us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.560s 1999.823us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 7.180s 393.309us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 18.160s 4037.563us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 5.660s 823.001us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 13.070s 2108.150us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.260s 137.665us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.900s 177.011us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.710s 1252.790us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.710s 1252.790us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.640s 136.792us 1 1 100.00
otp_ctrl_csr_rw 1.420s 42.915us 1 1 100.00
otp_ctrl_csr_aliasing 3.590s 243.549us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.900s 68.541us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.640s 136.792us 1 1 100.00
otp_ctrl_csr_rw 1.420s 42.915us 1 1 100.00
otp_ctrl_csr_aliasing 3.590s 243.549us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.900s 68.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_tl_intg_err 15.770s 2090.299us 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 15.770s 2090.299us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 6.630s 430.253us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 6.630s 430.253us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.560s 1999.823us 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.560s 1999.823us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.560s 1999.823us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.560s 1999.823us 1 1 100.00
otp_ctrl_macro_errs 18.160s 4037.563us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.560s 1999.823us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.560s 1999.823us 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.560s 1999.823us 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.560s 1999.823us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.560s 1999.823us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.560s 1999.823us 1 1 100.00
otp_ctrl_macro_errs 18.160s 4037.563us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.560s 1999.823us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.560s 1999.823us 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 2.810s 380.432us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 8.780s 513.185us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 10.500s 1335.240us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 10.500s 1335.240us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 10.500s 1335.240us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 10.500s 1335.240us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 10.500s 1335.240us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 6.630s 430.253us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 10.500s 1335.240us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 6.630s 430.253us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.790s 167368.136us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 6.780s 539.088us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 6.630s 430.253us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 6.630s 430.253us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 18.160s 4037.563us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 11.600s 5915.625us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.580s 27.863us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_csr_mem_rw_with_rand_reset 93064971061092833335471877554457498972874022751637477243188438678385277273992 95
UVM_ERROR @ 77662380 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 77662380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55337275255557278568960653548219402998995851147620479825950645662764203035604 96
UVM_ERROR @ 27863326 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27863326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1308) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_init_fail 101088802727956190059342370387785055380992258759700154850243926518759661589052 1628
UVM_ERROR @ 380432259 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 380432259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 57964927988961301497270108225021017495582304120121981796882195271272094833348 4467
UVM_ERROR @ 513184913 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (742713450 [0x2c44e86a] vs 742713442 [0x2c44e862]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 513184913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---