Simulation Results: pattgen

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
93.75%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 7.000s 95.627us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 171.668us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 26.179us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 599.828us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 16.293us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 42.178us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 26.179us 1 1 100.00
pattgen_csr_aliasing 1.000s 16.293us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 20.000s 10628.356us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 28.000s 4178.120us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 45.373us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 2.000s 453.895us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 11.275us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 2.000s 15.299us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 3.000s 433.924us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 3.000s 433.924us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 171.668us 1 1 100.00
pattgen_csr_rw 1.000s 26.179us 1 1 100.00
pattgen_csr_aliasing 1.000s 16.293us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 43.133us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 171.668us 1 1 100.00
pattgen_csr_rw 1.000s 26.179us 1 1 100.00
pattgen_csr_aliasing 1.000s 16.293us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 43.133us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 2.000s 276.713us 1 1 100.00
pattgen_tl_intg_err 2.000s 78.892us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 78.892us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 33.000s 1247.306us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 18.000s 10089.817us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17)
pattgen_inactive_level 46768160817229090082504340251732219038276401636480832679357976280285073129896 96
UVM_FATAL @ 10089817410 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x816aa7d0, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10089817410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 38430346313222833585984207246074485112469793140064908055557624430696890690951 149
UVM_ERROR @ 591498525 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 591498562 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 591498562 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 591549067 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:
pattgen_stress_all 96910994784708737360236404220370126260388538399965306068854850836645077354727 145
UVM_ERROR @ 453894972 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10183