Simulation Results: rom_ctrl

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.86 %
  • code
  • 98.18 %
  • assert
  • 95.49 %
  • func
  • 96.90 %
  • line
  • 99.46 %
  • branch
  • 98.54 %
  • cond
  • 93.61 %
  • toggle
  • 99.29 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.780s 1371.780us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.100s 393.189us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.900s 165.483us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.410s 213.853us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.250s 371.101us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.250s 311.689us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.900s 165.483us 1 1 100.00
rom_ctrl_csr_aliasing 3.250s 371.101us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.780s 288.415us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.890s 295.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.670s 296.227us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 16.070s 1099.215us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.860s 231.813us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.960s 1055.789us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.750s 557.378us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.750s 557.378us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.100s 393.189us 1 1 100.00
rom_ctrl_csr_rw 5.900s 165.483us 1 1 100.00
rom_ctrl_csr_aliasing 3.250s 371.101us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.150s 565.588us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.100s 393.189us 1 1 100.00
rom_ctrl_csr_rw 5.900s 165.483us 1 1 100.00
rom_ctrl_csr_aliasing 3.250s 371.101us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.150s 565.588us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.380s 9978.790us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.970s 578.228us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 198.180s 975.868us 0 1 0.00
rom_ctrl_tl_intg_err 43.160s 2894.091us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 198.180s 975.868us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 198.180s 975.868us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.380s 9978.790us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.380s 9978.790us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.380s 9978.790us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.380s 9978.790us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.380s 9978.790us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 198.180s 975.868us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 198.180s 975.868us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.780s 1371.780us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.780s 1371.780us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.780s 1371.780us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 43.160s 2894.091us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.380s 9978.790us 1 1 100.00
rom_ctrl_kmac_err_chk 6.860s 231.813us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.380s 9978.790us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.380s 9978.790us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.380s 9978.790us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.970s 578.228us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 198.180s 975.868us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 48.040s 1982.279us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
rom_ctrl_sec_cm 101263336690351668628669962404542523261031694301268112691372214668015836989919 105
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 4105086ps failed at 4105086ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 7795121ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 7795121ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))