Simulation Results: rom_ctrl

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.26 %
  • code
  • 96.50 %
  • assert
  • 95.49 %
  • func
  • 93.79 %
  • line
  • 99.32 %
  • branch
  • 97.45 %
  • cond
  • 92.87 %
  • toggle
  • 99.54 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 9.110s 305.131us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 13.700s 1033.545us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.210s 212.434us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.210s 523.168us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.010s 208.378us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.400s 304.415us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.210s 212.434us 1 1 100.00
rom_ctrl_csr_aliasing 6.010s 208.378us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.580s 372.933us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.340s 211.632us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 10.280s 8353.887us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 29.950s 4211.954us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.350s 399.649us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 9.500s 1027.732us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.180s 1028.732us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.180s 1028.732us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 13.700s 1033.545us 1 1 100.00
rom_ctrl_csr_rw 6.210s 212.434us 1 1 100.00
rom_ctrl_csr_aliasing 6.010s 208.378us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.110s 206.858us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 13.700s 1033.545us 1 1 100.00
rom_ctrl_csr_rw 6.210s 212.434us 1 1 100.00
rom_ctrl_csr_aliasing 6.010s 208.378us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.110s 206.858us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.130s 3237.338us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 23.040s 1469.379us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 443.550s 1217.596us 0 1 0.00
rom_ctrl_tl_intg_err 97.660s 886.345us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 443.550s 1217.596us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 443.550s 1217.596us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.130s 3237.338us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.130s 3237.338us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.130s 3237.338us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.130s 3237.338us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.130s 3237.338us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 443.550s 1217.596us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 443.550s 1217.596us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 9.110s 305.131us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 9.110s 305.131us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 9.110s 305.131us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 97.660s 886.345us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.130s 3237.338us 1 1 100.00
rom_ctrl_kmac_err_chk 13.350s 399.649us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.130s 3237.338us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.130s 3237.338us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.130s 3237.338us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 23.040s 1469.379us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 443.550s 1217.596us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 71.570s 4046.525us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 90476930720160936461893322497923756472051101300776855308594291596073519107747 241
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 33009079ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 33009079ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 33009079ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))