Simulation Results: rstmgr

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.03 %
  • code
  • 99.36 %
  • assert
  • 97.72 %
  • func
  • 97.01 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.96 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.240s 250.167us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.740s 89.903us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.740s 84.780us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.490s 266.567us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.260s 252.912us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.940s 115.036us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.740s 84.780us 1 1 100.00
rstmgr_csr_aliasing 1.260s 252.912us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.700s 92.273us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.520s 138.289us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.980s 134.119us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.190s 948.755us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.190s 948.755us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.190s 948.755us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.190s 948.755us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 5.060s 1962.764us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.690s 71.249us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.140s 383.823us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.140s 383.823us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.740s 89.903us 1 1 100.00
rstmgr_csr_rw 0.740s 84.780us 1 1 100.00
rstmgr_csr_aliasing 1.260s 252.912us 1 1 100.00
rstmgr_same_csr_outstanding 1.280s 237.207us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.740s 89.903us 1 1 100.00
rstmgr_csr_rw 0.740s 84.780us 1 1 100.00
rstmgr_csr_aliasing 1.260s 252.912us 1 1 100.00
rstmgr_same_csr_outstanding 1.280s 237.207us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 9.940s 8495.354us 1 1 100.00
rstmgr_tl_intg_err 2.430s 951.293us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 9.940s 8495.354us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 9.940s 8495.354us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.430s 951.293us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.050s 143.117us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.420s 1276.829us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.060s 303.154us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 9.940s 8495.354us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.740s 84.780us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.740s 84.780us 1 1 100.00

Error Messages

   Test seed line log context