Simulation Results: rv_timer

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.18 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 94.71 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.030s 160.776us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.550s 15.515us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.560s 11.932us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.800s 235.098us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.770s 61.993us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.790s 18.645us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.560s 11.932us 1 1 100.00
rv_timer_csr_aliasing 0.770s 61.993us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.750s 803.425us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.100s 2114.332us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 139.650s 127733.174us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 139.650s 127733.174us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.120s 9777.968us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.560s 74.826us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.560s 16.936us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.950s 348.978us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.950s 348.978us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 15.515us 1 1 100.00
rv_timer_csr_rw 0.560s 11.932us 1 1 100.00
rv_timer_csr_aliasing 0.770s 61.993us 1 1 100.00
rv_timer_same_csr_outstanding 0.710s 108.959us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 15.515us 1 1 100.00
rv_timer_csr_rw 0.560s 11.932us 1 1 100.00
rv_timer_csr_aliasing 0.770s 61.993us 1 1 100.00
rv_timer_same_csr_outstanding 0.710s 108.959us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.900s 256.460us 1 1 100.00
rv_timer_tl_intg_err 1.060s 106.591us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.060s 106.591us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.700s 111.802us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.680s 44.590us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 17.470s 4094.675us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 33875430114766088459134255077598324683994909295545683244283237252784468869665 72
UVM_FATAL @ 111801522 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd24e3704) == 0x1
UVM_INFO @ 111801522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 24405492515017021724807585376222152078553246699737714198579069190461012782490 73
UVM_FATAL @ 803424807 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x57ef3504) == 0x1
UVM_INFO @ 803424807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 50795485724281086058039858355205839980833137071219356431875383327100130108063 72
UVM_ERROR @ 44589930 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 44589930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---