Simulation Results: spi_device

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.30 %
  • code
  • 93.21 %
  • assert
  • 94.30 %
  • func
  • 74.40 %
  • line
  • 99.09 %
  • branch
  • 98.35 %
  • cond
  • 95.73 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 210.960s 38188.203us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.870s 81.254us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.260s 125.752us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 23.760s 6471.337us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 11.270s 11963.181us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.560s 59.926us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.260s 125.752us 1 1 100.00
spi_device_csr_aliasing 11.270s 11963.181us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.650s 12.152us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.100s 53.526us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.760s 15.585us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.830s 1.183us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.810s 3.066us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.010s 671.752us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.010s 671.752us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 5.950s 11054.482us 1 1 100.00
spi_device_tpm_sts_read 0.890s 150.339us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 19.450s 98060.592us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.750s 93.060us 1 1 100.00
spi_device_flash_all 67.480s 5684.774us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.400s 295.143us 1 1 100.00
spi_device_flash_all 67.480s 5684.774us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.400s 295.143us 1 1 100.00
spi_device_flash_all 67.480s 5684.774us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 67.480s 5684.774us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.740s 835.745us 1 1 100.00
spi_device_flash_all 67.480s 5684.774us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.740s 835.745us 1 1 100.00
spi_device_flash_all 67.480s 5684.774us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.740s 835.745us 1 1 100.00
spi_device_flash_all 67.480s 5684.774us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.740s 835.745us 1 1 100.00
spi_device_flash_all 67.480s 5684.774us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.740s 835.745us 1 1 100.00
spi_device_flash_all 67.480s 5684.774us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.790s 321.780us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 6.430s 3228.625us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 6.430s 3228.625us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 6.430s 3228.625us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 21.280s 7631.600us 1 1 100.00
spi_device_read_buffer_direct 3.160s 257.947us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 6.430s 3228.625us 1 1 100.00
spi_device_flash_all 67.480s 5684.774us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 67.480s 5684.774us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 67.480s 5684.774us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.320s 210.260us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.320s 210.260us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 210.960s 38188.203us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 16.480s 7011.019us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 207.910s 68408.812us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.690s 35.365us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.790s 57.996us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.400s 24.497us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.400s 24.497us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.870s 81.254us 1 1 100.00
spi_device_csr_rw 2.260s 125.752us 1 1 100.00
spi_device_csr_aliasing 11.270s 11963.181us 1 1 100.00
spi_device_same_csr_outstanding 1.510s 117.839us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.870s 81.254us 1 1 100.00
spi_device_csr_rw 2.260s 125.752us 1 1 100.00
spi_device_csr_aliasing 11.270s 11963.181us 1 1 100.00
spi_device_same_csr_outstanding 1.510s 117.839us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.880s 329.148us 1 1 100.00
spi_device_tl_intg_err 15.490s 4197.652us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 15.490s 4197.652us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 10.740s 5811.260us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 107089731147615880925816573685481145582427536955481302675245220090957802145669 73
UVM_ERROR @ 995026 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[61])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 995026 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 995026 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[957])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 111116145199563346594471133055363081906968261021059844315558111154379317665898 73
UVM_ERROR @ 769868 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfec28b [111111101100001010001011] vs 0x0 [0])
UVM_ERROR @ 852868 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x470c73 [10001110000110001110011] vs 0x0 [0])
UVM_ERROR @ 952868 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa12dfb [101000010010110111111011] vs 0x0 [0])
UVM_ERROR @ 1021868 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2aba59 [1010101011101001011001] vs 0x0 [0])
UVM_ERROR @ 1054868 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x622663 [11000100010011001100011] vs 0x0 [0])