Simulation Results: spi_device

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.62 %
  • code
  • 94.19 %
  • assert
  • 94.27 %
  • func
  • 74.40 %
  • line
  • 99.14 %
  • branch
  • 98.42 %
  • cond
  • 96.29 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 431.120s 291302.682us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.120s 46.114us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.350s 386.428us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 23.600s 2084.016us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 11.040s 2513.501us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.440s 776.909us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.350s 386.428us 1 1 100.00
spi_device_csr_aliasing 11.040s 2513.501us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.880s 14.302us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.820s 56.090us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.760s 16.579us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.000s 34.026us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.820s 26.689us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.560s 573.551us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.560s 573.551us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 8.980s 19080.951us 1 1 100.00
spi_device_tpm_sts_read 0.820s 18.833us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 13.990s 3844.267us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 10.460s 78174.313us 1 1 100.00
spi_device_flash_all 5.140s 1018.935us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 17.760s 11237.413us 1 1 100.00
spi_device_flash_all 5.140s 1018.935us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 17.760s 11237.413us 1 1 100.00
spi_device_flash_all 5.140s 1018.935us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 5.140s 1018.935us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 9.800s 5574.621us 1 1 100.00
spi_device_flash_all 5.140s 1018.935us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 9.800s 5574.621us 1 1 100.00
spi_device_flash_all 5.140s 1018.935us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 9.800s 5574.621us 1 1 100.00
spi_device_flash_all 5.140s 1018.935us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 9.800s 5574.621us 1 1 100.00
spi_device_flash_all 5.140s 1018.935us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 9.800s 5574.621us 1 1 100.00
spi_device_flash_all 5.140s 1018.935us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 6.690s 2410.631us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 9.720s 1800.621us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 9.720s 1800.621us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 9.720s 1800.621us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 10.340s 6490.585us 1 1 100.00
spi_device_read_buffer_direct 2.890s 908.514us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 9.720s 1800.621us 1 1 100.00
spi_device_flash_all 5.140s 1018.935us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 5.140s 1018.935us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 5.140s 1018.935us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.930s 3279.040us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.930s 3279.040us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 431.120s 291302.682us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 27.080s 4872.839us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 121.800s 82662.794us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.800s 42.180us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.710s 17.112us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.870s 819.246us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.870s 819.246us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.120s 46.114us 1 1 100.00
spi_device_csr_rw 2.350s 386.428us 1 1 100.00
spi_device_csr_aliasing 11.040s 2513.501us 1 1 100.00
spi_device_same_csr_outstanding 2.850s 395.498us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.120s 46.114us 1 1 100.00
spi_device_csr_rw 2.350s 386.428us 1 1 100.00
spi_device_csr_aliasing 11.040s 2513.501us 1 1 100.00
spi_device_same_csr_outstanding 2.850s 395.498us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.010s 131.118us 1 1 100.00
spi_device_tl_intg_err 9.300s 204.361us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 9.300s 204.361us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 113.260s 59151.104us 1 1 100.00

Error Messages

   Test seed line log context