Simulation Results: sram_ctrl

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.98 %
  • code
  • 88.16 %
  • assert
  • 95.41 %
  • func
  • 95.36 %
  • line
  • 97.05 %
  • branch
  • 94.80 %
  • cond
  • 91.55 %
  • toggle
  • 90.71 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 38.150s 1931.321us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.760s 41.580us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.730s 13.638us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 0.940s 26.421us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 24.320us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.330s 351.758us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.730s 13.638us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 24.320us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 102.030s 2716.424us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 106.490s 9140.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 352.190s 62044.200us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 207.690s 4925.554us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 462.970s 39637.524us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 362.910s 10908.704us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 28.810s 17841.353us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 36.260s 12294.301us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 13.020s 1209.516us 1 1 100.00
sram_ctrl_partial_access_b2b 372.180s 99078.620us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 31.400s 3119.647us 1 1 100.00
sram_ctrl_throughput_w_partial_write 13.110s 730.814us 1 1 100.00
sram_ctrl_throughput_w_readback 15.770s 828.117us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 235.790s 5090.472us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.850s 682.836us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 3231.960s 609846.123us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.710s 47.457us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.850s 121.150us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.850s 121.150us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.760s 41.580us 1 1 100.00
sram_ctrl_csr_rw 0.730s 13.638us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 24.320us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.760s 17.443us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.760s 41.580us 1 1 100.00
sram_ctrl_csr_rw 0.730s 13.638us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 24.320us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.760s 17.443us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 16.370s 7697.801us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.600s 2.196us 0 1 0.00
sram_ctrl_tl_intg_err 1.230s 115.661us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.600s 2.196us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.230s 115.661us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 235.790s 5090.472us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 235.790s 5090.472us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.730s 13.638us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 36.260s 12294.301us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 36.260s 12294.301us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 36.260s 12294.301us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 28.810s 17841.353us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.490s 2301.424us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 16.370s 7697.801us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.630s 1352.243us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 38.150s 1931.321us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 38.150s 1931.321us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 36.260s 12294.301us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.600s 2.196us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 28.810s 17841.353us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.600s 2.196us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.600s 2.196us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 38.150s 1931.321us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.600s 2.196us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 8.730s 503.198us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 68376677994610153615498526041417361473835415809693942363835252709167079534239 97
UVM_ERROR @ 2195718 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 2195718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---