Simulation Results: sram_ctrl

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.32 %
  • code
  • 95.87 %
  • assert
  • 95.09 %
  • func
  • 94.99 %
  • line
  • 99.07 %
  • branch
  • 97.47 %
  • cond
  • 92.29 %
  • toggle
  • 90.50 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 10.790s 458.130us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.740s 40.014us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.680s 16.359us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.470s 240.179us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.770s 25.178us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 0.940s 61.640us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.680s 16.359us 1 1 100.00
sram_ctrl_csr_aliasing 0.770s 25.178us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.270s 947.029us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.670s 212.691us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 270.810s 46392.891us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 156.450s 43335.555us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 28.990s 668.388us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 369.460s 2969.402us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 2.670s 1375.602us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 502.770s 65521.732us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 23.830s 1074.879us 1 1 100.00
sram_ctrl_partial_access_b2b 126.780s 2436.416us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 6.420s 68.091us 1 1 100.00
sram_ctrl_throughput_w_partial_write 20.820s 114.589us 1 1 100.00
sram_ctrl_throughput_w_readback 27.390s 507.412us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 301.910s 5252.739us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.690s 27.703us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 975.130s 32351.591us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.750s 36.722us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.840s 444.307us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.840s 444.307us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.740s 40.014us 1 1 100.00
sram_ctrl_csr_rw 0.680s 16.359us 1 1 100.00
sram_ctrl_csr_aliasing 0.770s 25.178us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.700s 30.053us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.740s 40.014us 1 1 100.00
sram_ctrl_csr_rw 0.680s 16.359us 1 1 100.00
sram_ctrl_csr_aliasing 0.770s 25.178us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.700s 30.053us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.470s 480.821us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.700s 1.004us 0 1 0.00
sram_ctrl_tl_intg_err 2.180s 392.526us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.700s 1.004us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.180s 392.526us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 301.910s 5252.739us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 301.910s 5252.739us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.680s 16.359us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 502.770s 65521.732us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 502.770s 65521.732us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 502.770s 65521.732us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 2.670s 1375.602us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 0.860s 86.999us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.470s 480.821us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.790s 28.200us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 10.790s 458.130us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 10.790s 458.130us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 502.770s 65521.732us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.700s 1.004us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 2.670s 1375.602us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.700s 1.004us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.700s 1.004us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 10.790s 458.130us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.700s 1.004us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 42.170s 2328.325us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 76953686211314510583965619126605268289165698551469148120730019085244687465575 96
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 1003871 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 1003871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---