Simulation Results: sysrst_ctrl

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.10 %
  • code
  • 93.73 %
  • assert
  • 94.44 %
  • func
  • 67.14 %
  • line
  • 97.75 %
  • branch
  • 97.63 %
  • cond
  • 95.69 %
  • toggle
  • 100.00 %
  • FSM
  • 77.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.520s 2136.672us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.840s 2473.569us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.650s 2401.680us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.810s 2367.264us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 8.610s 4033.505us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.900s 2060.953us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 123.620s 75989.879us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 5.770s 2145.736us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.650s 2064.334us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.900s 2060.953us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.770s 2145.736us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 149.670s 120071.658us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 55.220s 111854.403us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 58.190s 129254.688us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 3.410s 3214.319us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.000s 2516.599us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.580s 2155.456us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 11.210s 5162.400us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.620s 2612.210us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.800s 5087.802us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 16.190s 35049.106us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 11.670s 6486.823us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.620s 2035.607us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 5.540s 2011.531us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 1.710s 2207.183us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 1.710s 2207.183us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 8.610s 4033.505us 1 1 100.00
sysrst_ctrl_csr_rw 1.900s 2060.953us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.770s 2145.736us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 7.430s 9869.675us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 8.610s 4033.505us 1 1 100.00
sysrst_ctrl_csr_rw 1.900s 2060.953us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.770s 2145.736us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 7.430s 9869.675us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 20.020s 22104.266us 1 1 100.00
sysrst_ctrl_tl_intg_err 11.850s 22387.869us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 11.850s 22387.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 7.710s 7586.006us 1 1 100.00

Error Messages

   Test seed line log context