Simulation Results: uart

 
11/12/2025 17:35:48 sha: 6dd517f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.36 %
  • code
  • 96.80 %
  • assert
  • 97.12 %
  • func
  • 62.15 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 98.02 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 0.950s 327.237us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.580s 44.210us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.610s 12.879us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.120s 96.702us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.680s 60.455us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.690s 134.078us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.610s 12.879us 1 1 100.00
uart_csr_aliasing 0.680s 60.455us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 7.980s 24035.467us 1 1 100.00
parity 2 2 100.00
uart_smoke 0.950s 327.237us 1 1 100.00
uart_tx_rx 7.980s 24035.467us 1 1 100.00
parity_error 2 2 100.00
uart_intr 19.260s 81501.223us 1 1 100.00
uart_rx_parity_err 48.270s 74859.620us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 7.980s 24035.467us 1 1 100.00
uart_intr 19.260s 81501.223us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 48.250s 205496.882us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 68.830s 117880.003us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 18.350s 89872.500us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 19.260s 81501.223us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 19.260s 81501.223us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 19.260s 81501.223us 1 1 100.00
perf 1 1 100.00
uart_perf 77.840s 12807.489us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.670s 1226.381us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.670s 1226.381us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 7.230s 7362.352us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 46.880s 44520.026us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 0.920s 492.559us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 39.200s 6653.372us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 206.630s 127075.433us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 735.800s 240900.217us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.560s 22.916us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.590s 18.498us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.700s 142.539us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.700s 142.539us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.580s 44.210us 1 1 100.00
uart_csr_rw 0.610s 12.879us 1 1 100.00
uart_csr_aliasing 0.680s 60.455us 1 1 100.00
uart_same_csr_outstanding 0.680s 27.810us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.580s 44.210us 1 1 100.00
uart_csr_rw 0.610s 12.879us 1 1 100.00
uart_csr_aliasing 0.680s 60.455us 1 1 100.00
uart_same_csr_outstanding 0.680s 27.810us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.730s 38.682us 1 1 100.00
uart_tl_intg_err 1.030s 110.073us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.030s 110.073us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 18.510s 15211.319us 1 1 100.00

Error Messages

   Test seed line log context