Simulation Results: adc_ctrl

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 77.56 %
  • code
  • 96.43 %
  • assert
  • 95.62 %
  • func
  • 40.64 %
  • line
  • 99.02 %
  • branch
  • 98.51 %
  • cond
  • 95.45 %
  • toggle
  • 100.00 %
  • FSM
  • 89.19 %
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 5.600s 5630.952us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 0.850s 1093.214us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.390s 586.646us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 40.210s 27982.088us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.670s 795.619us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.510s 556.925us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.390s 586.646us 1 1 100.00
adc_ctrl_csr_aliasing 1.670s 795.619us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 66.980s 162658.000us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 833.990s 490703.946us 1 1 100.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 271.740s 168209.484us 0 1 0.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 103.130s 335263.319us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 365.160s 218635.603us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 62.340s 386181.837us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 468.490s 363899.194us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 295.330s 173946.089us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 7.360s 4272.661us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 46.260s 25988.470us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 141.340s 83232.183us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 114.770s 538947.982us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.180s 549.282us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.900s 443.268us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.240s 716.047us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.240s 716.047us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.850s 1093.214us 1 1 100.00
adc_ctrl_csr_rw 1.390s 586.646us 1 1 100.00
adc_ctrl_csr_aliasing 1.670s 795.619us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.480s 4820.223us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.850s 1093.214us 1 1 100.00
adc_ctrl_csr_rw 1.390s 586.646us 1 1 100.00
adc_ctrl_csr_aliasing 1.670s 795.619us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.480s 4820.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 6.570s 3737.108us 1 1 100.00
adc_ctrl_tl_intg_err 4.010s 9795.284us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 4.010s 9795.284us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 5.380s 6006.571us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state
adc_ctrl_filters_interrupt 92839388497383903936393461792735109274102504962782474160282589420944508029814 318
UVM_ERROR @ 168209484249 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 168209484249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---