Simulation Results: aes

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.55 %
  • code
  • 87.85 %
  • assert
  • 97.75 %
  • func
  • 80.04 %
  • block
  • 89.84 %
  • line
  • 92.14 %
  • branch
  • 80.33 %
  • toggle
  • 97.99 %
  • FSM
  • 80.95 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 94.519us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 199.699us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 74.415us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 57.245us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 123.122us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 237.848us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 65.504us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 57.245us 1 1 100.00
aes_csr_aliasing 2.000s 237.848us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 199.699us 1 1 100.00
aes_config_error 3.000s 124.853us 1 1 100.00
aes_stress 3.000s 56.713us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 199.699us 1 1 100.00
aes_config_error 3.000s 124.853us 1 1 100.00
aes_stress 3.000s 56.713us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 56.713us 1 1 100.00
aes_b2b 5.000s 678.507us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 56.713us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 199.699us 1 1 100.00
aes_config_error 3.000s 124.853us 1 1 100.00
aes_stress 3.000s 56.713us 1 1 100.00
aes_alert_reset 3.000s 76.350us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 67.719us 1 1 100.00
aes_config_error 3.000s 124.853us 1 1 100.00
aes_alert_reset 3.000s 76.350us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 441.375us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 110.227us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 76.350us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 56.713us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 56.713us 1 1 100.00
aes_sideload 2.000s 80.345us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 83.262us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 20.000s 709.546us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 3.000s 91.726us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 81.679us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 81.679us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 74.415us 1 1 100.00
aes_csr_rw 2.000s 57.245us 1 1 100.00
aes_csr_aliasing 2.000s 237.848us 1 1 100.00
aes_same_csr_outstanding 2.000s 68.184us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 74.415us 1 1 100.00
aes_csr_rw 2.000s 57.245us 1 1 100.00
aes_csr_aliasing 2.000s 237.848us 1 1 100.00
aes_same_csr_outstanding 2.000s 68.184us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 253.639us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 2.000s 113.627us 1 1 100.00
aes_control_fi 1.000s 47.293us 1 1 100.00
aes_cipher_fi 2.000s 54.675us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 894.884us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 894.884us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 894.884us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 894.884us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 330.692us 1 1 100.00
tl_intg_err 2 2 100.00
aes_tl_intg_err 2.000s 452.195us 1 1 100.00
aes_sec_cm 6.000s 5451.841us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 452.195us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 76.350us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 894.884us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 894.884us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 199.699us 1 1 100.00
aes_stress 3.000s 56.713us 1 1 100.00
aes_alert_reset 3.000s 76.350us 1 1 100.00
aes_core_fi 3.000s 71.013us 1 1 100.00
sec_cm_gcm_config_sparse 2 2 100.00
aes_config_error 3.000s 124.853us 1 1 100.00
aes_stress 3.000s 56.713us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 894.884us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 65.801us 1 1 100.00
aes_stress 3.000s 56.713us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 56.713us 1 1 100.00
aes_sideload 2.000s 80.345us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 65.801us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 65.801us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 65.801us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 65.801us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 65.801us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 56.713us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 56.713us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 2.000s 113.627us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 2.000s 113.627us 1 1 100.00
aes_control_fi 1.000s 47.293us 1 1 100.00
aes_cipher_fi 2.000s 54.675us 1 1 100.00
aes_ctr_fi 3.000s 90.512us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 2.000s 113.627us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 2.000s 113.627us 1 1 100.00
aes_control_fi 1.000s 47.293us 1 1 100.00
aes_cipher_fi 2.000s 54.675us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 54.675us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 2.000s 113.627us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 2.000s 113.627us 1 1 100.00
aes_control_fi 1.000s 47.293us 1 1 100.00
aes_ctr_fi 3.000s 90.512us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 2.000s 113.627us 1 1 100.00
aes_control_fi 1.000s 47.293us 1 1 100.00
aes_cipher_fi 2.000s 54.675us 1 1 100.00
aes_ctr_fi 3.000s 90.512us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 76.350us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 2.000s 113.627us 1 1 100.00
aes_control_fi 1.000s 47.293us 1 1 100.00
aes_cipher_fi 2.000s 54.675us 1 1 100.00
aes_ctr_fi 3.000s 90.512us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 2.000s 113.627us 1 1 100.00
aes_control_fi 1.000s 47.293us 1 1 100.00
aes_cipher_fi 2.000s 54.675us 1 1 100.00
aes_ctr_fi 3.000s 90.512us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 2.000s 113.627us 1 1 100.00
aes_control_fi 1.000s 47.293us 1 1 100.00
aes_ctr_fi 3.000s 90.512us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 2.000s 113.627us 1 1 100.00
aes_control_fi 1.000s 47.293us 1 1 100.00
aes_cipher_fi 2.000s 54.675us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 5.000s 384.833us 0 1 0.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1122): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS)
aes_stress_all_with_rand_reset 23653745296427885659065090200352927901084309245266751437956965907328879605475 409
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,1122): (time 384832873 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 384792873 PS)
UVM_ERROR @ 384832873 ps: (aes_core.sv:1122) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
UVM_INFO @ 384832873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---