Simulation Results: alert_handler

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.61 %
  • code
  • 93.07 %
  • assert
  • 98.33 %
  • func
  • 77.44 %
  • line
  • 99.72 %
  • branch
  • 99.79 %
  • cond
  • 94.83 %
  • toggle
  • 93.61 %
  • FSM
  • 77.42 %
Validation stages
V1
100.00%
V2
91.67%
V2S
96.30%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 13.050s 1378.178us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.820s 54.936us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.250s 202.962us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 130.400s 6532.882us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 72.550s 19033.319us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.250s 993.065us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.250s 202.962us 1 1 100.00
alert_handler_csr_aliasing 72.550s 19033.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 54.320s 4690.080us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 14.000s 1633.524us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1538.380s 37756.430us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 16.610s 897.293us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 13.050s 1378.178us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 8.790s 351.535us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 24.040s 806.120us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 6.010s 306.949us 0 1 0.00
lpg 1 2 50.00
alert_handler_lpg 324.380s 8834.607us 0 1 0.00
alert_handler_lpg_stub_clk 978.000s 100074.487us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2001.380s 55534.937us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 26.820s 899.474us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.420s 28.532us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.790s 21.312us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 12.390s 270.596us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 12.390s 270.596us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.820s 54.936us 1 1 100.00
alert_handler_csr_rw 4.250s 202.962us 1 1 100.00
alert_handler_csr_aliasing 72.550s 19033.319us 1 1 100.00
alert_handler_same_csr_outstanding 27.120s 2697.992us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.820s 54.936us 1 1 100.00
alert_handler_csr_rw 4.250s 202.962us 1 1 100.00
alert_handler_csr_aliasing 72.550s 19033.319us 1 1 100.00
alert_handler_same_csr_outstanding 27.120s 2697.992us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 130.940s 3186.428us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 130.940s 3186.428us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 130.940s 3186.428us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 130.940s 3186.428us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 621.550s 19061.068us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 15.150s 1758.038us 1 1 100.00
alert_handler_tl_intg_err 2.930s 57.410us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.930s 57.410us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 130.940s 3186.428us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 13.050s 1378.178us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 13.050s 1378.178us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 13.050s 1378.178us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 13.050s 1378.178us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 16.610s 897.293us 1 1 100.00
sec_cm_lpg_intersig_mubi 0 1 0.00
alert_handler_lpg 324.380s 8834.607us 0 1 0.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 16.610s 897.293us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1538.380s 37756.430us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1538.380s 37756.430us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.150s 1758.038us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.150s 1758.038us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.150s 1758.038us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.150s 1758.038us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 15.150s 1758.038us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.150s 1758.038us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.150s 1758.038us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.150s 1758.038us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 15.150s 1758.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 37.730s 1003.239us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:595) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (* [*] vs * [*])
alert_handler_ping_timeout 56177272481804520426459826452186268434931894328409215757419314638245024486424 78
UVM_ERROR @ 306948535 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 306948535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:483) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_lpg 54910240708118742536870605317852689014160131078865701134372557758889997745083 77
UVM_ERROR @ 8834607285 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 8834607285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 56652756551105658072649783208065724552982240174908308197722102162501799311785 103
UVM_ERROR @ 1003238890 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1003238890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---