Simulation Results: chip

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.48 %
  • code
  • 85.29 %
  • assert
  • 96.60 %
  • func
  • 41.55 %
  • line
  • 94.27 %
  • branch
  • 93.69 %
  • cond
  • 89.86 %
  • toggle
  • 91.50 %
  • FSM
  • 57.14 %
Validation stages
V1
95.65%
V2
84.80%
V2S
100.00%
V3
63.33%
unmapped
62.50%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 151.280s 2858.616us 1 1 100.00
chip_sw_example_rom 72.120s 2576.920us 1 1 100.00
chip_sw_example_manufacturer 87.960s 2866.048us 1 1 100.00
chip_sw_example_concurrency 139.590s 3054.387us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 203.480s 7040.440us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 187.360s 4307.786us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 457.700s 7106.066us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3727.500s 32577.392us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 53.210s 2940.740us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3727.500s 32577.392us 1 1 100.00
chip_csr_rw 187.360s 4307.786us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 5.650s 157.021us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 237.520s 4392.242us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 237.520s 4392.242us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 237.520s 4392.242us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 401.210s 4462.678us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 401.210s 4462.678us 1 1 100.00
chip_sw_uart_tx_rx_idx1 384.640s 4764.752us 1 1 100.00
chip_sw_uart_tx_rx_idx2 367.640s 4077.826us 1 1 100.00
chip_sw_uart_tx_rx_idx3 309.440s 4109.830us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 301.850s 3706.405us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 361.500s 3989.086us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 255.990s 4578.855us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 160.760s 4963.770us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 160.760s 4963.770us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 180.660s 2739.846us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 146.510s 2804.994us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 134.540s 3585.232us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 191.370s 3438.397us 1 1 100.00
chip_tap_straps_testunlock0 293.090s 5197.949us 1 1 100.00
chip_tap_straps_rma 131.740s 3195.415us 1 1 100.00
chip_tap_straps_prod 885.690s 15091.908us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 154.340s 3635.306us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 809.720s 8722.559us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 469.130s 6046.027us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 469.130s 6046.027us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 547.070s 7705.764us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1087.220s 13562.860us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 415.970s 4377.900us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 567.290s 6159.516us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3433.600s 19909.023us 1 1 100.00
chip_sw_aes_enc_jitter_en 131.740s 2678.922us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 662.740s 7040.568us 1 1 100.00
chip_sw_hmac_enc_jitter_en 123.790s 3153.781us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 922.080s 9190.429us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 169.130s 3055.228us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 301.810s 3986.528us 1 1 100.00
chip_sw_clkmgr_jitter 123.490s 2971.421us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 233.880s 3075.265us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 472.160s 6098.059us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 309.440s 5822.350us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 184.850s 3326.557us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 309.440s 5822.350us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 115.040s 2717.228us 1 1 100.00
chip_sw_aes_smoketest 124.690s 2578.532us 1 1 100.00
chip_sw_aon_timer_smoketest 167.310s 2915.143us 1 1 100.00
chip_sw_clkmgr_smoketest 133.840s 2789.129us 1 1 100.00
chip_sw_csrng_smoketest 166.510s 2711.521us 1 1 100.00
chip_sw_entropy_src_smoketest 595.060s 5515.577us 1 1 100.00
chip_sw_gpio_smoketest 183.440s 3117.736us 1 1 100.00
chip_sw_hmac_smoketest 173.070s 3144.262us 1 1 100.00
chip_sw_kmac_smoketest 152.790s 2918.600us 1 1 100.00
chip_sw_otbn_smoketest 1130.500s 10008.154us 1 1 100.00
chip_sw_pwrmgr_smoketest 240.290s 5493.036us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 275.940s 6264.563us 1 1 100.00
chip_sw_rv_plic_smoketest 139.620s 2938.244us 1 1 100.00
chip_sw_rv_timer_smoketest 154.820s 2617.431us 1 1 100.00
chip_sw_rstmgr_smoketest 113.830s 2834.076us 1 1 100.00
chip_sw_sram_ctrl_smoketest 137.650s 3203.857us 1 1 100.00
chip_sw_uart_smoketest 121.470s 2801.361us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 113.340s 3137.081us 1 1 100.00
chip_sw_rom_functests 1 1 100.00
rom_keymgr_functest 339.730s 5255.614us 1 1 100.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7713.170s 62160.820us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2387.620s 14273.424us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 166.770s 6230.695us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 161.450s 3535.733us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 232.780s 3906.305us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6772.660s 53331.469us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7043.940s 58060.626us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 51.880s 2448.128us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 51.880s 2448.128us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3727.500s 32577.392us 1 1 100.00
chip_same_csr_outstanding 2680.720s 30062.012us 1 1 100.00
chip_csr_hw_reset 203.480s 7040.440us 1 1 100.00
chip_csr_rw 187.360s 4307.786us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3727.500s 32577.392us 1 1 100.00
chip_same_csr_outstanding 2680.720s 30062.012us 1 1 100.00
chip_csr_hw_reset 203.480s 7040.440us 1 1 100.00
chip_csr_rw 187.360s 4307.786us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 28.570s 586.827us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.410s 41.763us 1 1 100.00
xbar_smoke_large_delays 47.700s 7619.653us 1 1 100.00
xbar_smoke_slow_rsp 47.820s 5599.534us 1 1 100.00
xbar_random_zero_delays 12.520s 219.232us 1 1 100.00
xbar_random_large_delays 324.700s 56641.839us 1 1 100.00
xbar_random_slow_rsp 214.710s 25617.012us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 21.830s 936.129us 1 1 100.00
xbar_error_and_unmapped_addr 24.500s 1158.983us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 25.560s 610.507us 1 1 100.00
xbar_error_and_unmapped_addr 24.500s 1158.983us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 26.070s 589.258us 1 1 100.00
xbar_access_same_device_slow_rsp 535.020s 63717.789us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 24.160s 1328.916us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 179.140s 3751.361us 1 1 100.00
xbar_stress_all_with_error 41.880s 960.890us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 226.600s 2798.461us 1 1 100.00
xbar_stress_all_with_reset_error 152.410s 1346.803us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2387.620s 14273.424us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2151.070s 29332.914us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2347.710s 16890.761us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 1958.030s 11741.683us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2395.750s 15451.710us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2485.220s 15552.294us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2543.550s 15445.960us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2428.430s 14270.763us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 26.020s 10.400us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 18.360s 10.120us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 18.240s 10.280us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 16.990s 10.100us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 17.110s 10.220us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 17.860s 10.300us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 17.140s 10.220us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 20.090s 10.280us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 26.110s 10.220us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 21.640s 10.340us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 16.620s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 20.370s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 16.420s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 22.160s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 16.920s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 16.240s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 25.340s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 17.080s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 17.400s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 18.320s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 17.400s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 17.140s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 16.880s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 17.260s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 16.020s 10.120us 0 1 0.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 1922.140s 12792.252us 1 1 100.00
rom_e2e_asm_init_dev 2521.610s 17972.644us 1 1 100.00
rom_e2e_asm_init_prod 2364.390s 15269.230us 1 1 100.00
rom_e2e_asm_init_prod_end 2348.940s 15115.494us 1 1 100.00
rom_e2e_asm_init_rma 2286.160s 14551.076us 1 1 100.00
rom_e2e_keymgr_init 1 3 33.33
rom_e2e_keymgr_init_rom_ext_meas 4312.750s 31071.244us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 2272.570s 15297.231us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 2252.200s 16660.362us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2409.050s 15889.409us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3062.970s 34593.272us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3062.970s 34593.272us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 195.880s 3101.514us 1 1 100.00
chip_sw_aes_enc_jitter_en 131.740s 2678.922us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 181.560s 3371.785us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 149.400s 2815.961us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1530.140s 10527.975us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 201.260s 3209.461us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 348.180s 5315.416us 1 1 100.00
chip_sw_all_escalation_resets 0 1 0.00
chip_sw_all_escalation_resets 171.150s 3313.478us 0 1 0.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 498.470s 5187.110us 1 1 100.00
chip_plic_all_irqs_10 223.850s 3567.373us 1 1 100.00
chip_plic_all_irqs_20 361.660s 4431.198us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 208.860s 3571.364us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 964.570s 9329.715us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 264.020s 3896.476us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 147.730s 2898.048us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 772.250s 6456.551us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 967.770s 7663.100us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 741.490s 7416.936us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8425.070s 255874.010us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 246.220s 3647.920us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 240.290s 5493.036us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 246.220s 3647.920us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 410.980s 8186.616us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 410.980s 8186.616us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 313.220s 6841.716us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 320.970s 5546.743us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 603.580s 5886.266us 1 1 100.00
chip_sw_aes_idle 149.400s 2815.961us 1 1 100.00
chip_sw_hmac_enc_idle 162.690s 3239.132us 1 1 100.00
chip_sw_kmac_idle 155.390s 3175.250us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 209.010s 3252.472us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 195.240s 4883.823us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 215.200s 4215.813us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 220.330s 4674.515us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 773.120s 9917.899us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 406.040s 4339.338us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 380.060s 4736.926us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 343.100s 3593.827us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 379.830s 4713.063us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 370.740s 4181.910us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 366.310s 4382.698us 1 1 100.00
chip_sw_ast_clk_outputs 547.070s 7705.764us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 243.590s 5679.837us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 343.100s 3593.827us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 379.830s 4713.063us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 415.970s 4377.900us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 567.290s 6159.516us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3433.600s 19909.023us 1 1 100.00
chip_sw_aes_enc_jitter_en 131.740s 2678.922us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 662.740s 7040.568us 1 1 100.00
chip_sw_hmac_enc_jitter_en 123.790s 3153.781us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 922.080s 9190.429us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 169.130s 3055.228us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 301.810s 3986.528us 1 1 100.00
chip_sw_clkmgr_jitter 123.490s 2971.421us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 109.070s 2777.706us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 366.560s 4231.642us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 569.410s 7261.060us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3001.540s 24508.621us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 118.780s 3203.994us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 120.120s 2753.796us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1027.590s 11180.673us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 134.300s 2698.152us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 307.940s 4193.503us 1 1 100.00
chip_sw_flash_init_reduced_freq 1132.270s 21990.415us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 2733.300s 27588.960us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 547.070s 7705.764us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 366.230s 4876.037us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 235.930s 3107.999us 1 1 100.00
chip_sw_clkmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 171.150s 3313.478us 0 1 0.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 772.250s 6456.551us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 731.640s 6776.139us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 129.180s 2756.781us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 327.390s 5894.554us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 160.540s 2564.125us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2233.760s 13582.419us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 162.980s 3410.895us 1 1 100.00
chip_sw_edn_entropy_reqs 786.200s 6322.610us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 162.980s 3410.895us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 731.640s 6776.139us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 130.160s 2898.798us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 918.010s 15478.777us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 561.350s 4974.564us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 567.290s 6159.516us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 300.350s 3556.599us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 415.970s 4377.900us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3482.510s 43952.276us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 918.010s 15478.777us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 217.250s 2971.099us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 617.260s 6497.036us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 237.060s 4485.331us 1 1 100.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3482.510s 43952.276us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 237.060s 4485.331us 1 1 100.00
chip_sw_flash_lc_iso_part_sw_rd_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 237.060s 4485.331us 1 1 100.00
chip_sw_flash_lc_iso_part_sw_wr_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 237.060s 4485.331us 1 1 100.00
chip_sw_flash_lc_seed_hw_rd_en 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 237.060s 4485.331us 1 1 100.00
chip_sw_flash_lc_escalate_en 0 1 0.00
chip_sw_all_escalation_resets 171.150s 3313.478us 0 1 0.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 154.030s 6469.429us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 563.430s 5219.991us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 283.770s 4445.673us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 283.770s 4445.673us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 202.530s 3543.425us 1 1 100.00
chip_sw_hmac_enc_jitter_en 123.790s 3153.781us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 162.690s 3239.132us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1247.480s 9548.094us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 701.530s 6009.515us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 406.580s 5240.180us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 443.940s 4879.671us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 370.220s 4931.175us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 218.710s 3595.718us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 617.260s 6497.036us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 922.080s 9190.429us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1613.180s 12021.230us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1530.140s 10527.975us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2051.480s 11404.233us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 151.890s 3048.624us 1 1 100.00
chip_sw_kmac_mode_kmac 182.700s 2956.239us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 169.130s 3055.228us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 617.260s 6497.036us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 545.720s 11200.980us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 166.970s 3230.370us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 917.190s 8262.472us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 155.390s 3175.250us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 348.180s 5315.416us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 191.370s 3438.397us 1 1 100.00
chip_tap_straps_rma 131.740s 3195.415us 1 1 100.00
chip_tap_straps_prod 885.690s 15091.908us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 143.410s 3319.641us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 545.720s 11200.980us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 545.720s 11200.980us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 545.720s 11200.980us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1294.740s 9944.583us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_prim_tl_access 154.030s 6469.429us 1 1 100.00
chip_rv_dm_lc_disabled 87.350s 3893.046us 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 237.060s 4485.331us 1 1 100.00
chip_sw_flash_rma_unlocked 3482.510s 43952.276us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 175.210s 3118.207us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 469.260s 7114.547us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 461.610s 6371.587us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 566.770s 6434.206us 0 1 0.00
chip_sw_lc_ctrl_transition 545.720s 11200.980us 1 1 100.00
chip_sw_keymgr_key_derivation 617.260s 6497.036us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 329.280s 9502.888us 1 1 100.00
chip_sw_sram_ctrl_execution_main 410.560s 7712.975us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 243.590s 5679.837us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 406.040s 4339.338us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 380.060s 4736.926us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 343.100s 3593.827us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 379.830s 4713.063us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 370.740s 4181.910us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 366.310s 4382.698us 1 1 100.00
chip_tap_straps_dev 191.370s 3438.397us 1 1 100.00
chip_tap_straps_rma 131.740s 3195.415us 1 1 100.00
chip_tap_straps_prod 885.690s 15091.908us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 123.900s 3326.514us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 97.090s 3690.298us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 95.530s 3151.811us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 97.990s 3718.568us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_rv_dm_lc_disabled 87.350s 3893.046us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1598.000s 33433.757us 1 1 100.00
chip_sw_lc_walkthrough 5 5 100.00
chip_sw_lc_walkthrough_dev 3766.580s 46634.545us 1 1 100.00
chip_sw_lc_walkthrough_prod 3478.640s 48841.204us 1 1 100.00
chip_sw_lc_walkthrough_prodend 477.590s 10959.687us 1 1 100.00
chip_sw_lc_walkthrough_rma 3868.210s 48829.559us 1 1 100.00
chip_sw_lc_walkthrough_testunlocks 1598.000s 33433.757us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 70.250s 2384.510us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 63.490s 1769.946us 1 1 100.00
rom_volatile_raw_unlock 71.540s 2466.372us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3241.220s 16860.426us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3433.600s 19909.023us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 603.580s 5886.266us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 603.580s 5886.266us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 603.580s 5886.266us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 290.850s 3824.148us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 545.720s 11200.980us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 918.010s 15478.777us 1 1 100.00
chip_sw_otbn_mem_scramble 290.850s 3824.148us 1 1 100.00
chip_sw_keymgr_key_derivation 617.260s 6497.036us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 328.950s 4386.516us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 178.260s 2444.891us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 918.010s 15478.777us 1 1 100.00
chip_sw_otbn_mem_scramble 290.850s 3824.148us 1 1 100.00
chip_sw_keymgr_key_derivation 617.260s 6497.036us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 328.950s 4386.516us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 178.260s 2444.891us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 545.720s 11200.980us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 230.930s 4809.463us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 143.410s 3319.641us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 154.030s 6469.429us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 175.210s 3118.207us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 469.260s 7114.547us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 461.610s 6371.587us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 566.770s 6434.206us 0 1 0.00
chip_sw_lc_ctrl_transition 545.720s 11200.980us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 154.030s 6469.429us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 782.620s 6337.371us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 330.680s 9157.331us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1116.930s 27885.988us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 281.220s 7745.088us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 355.070s 6920.974us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 342.340s 5774.278us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 954.530s 23162.263us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 203.340s 5896.562us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 410.980s 8186.616us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 830.760s 12570.322us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 262.340s 4615.841us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 330.680s 9157.331us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 270.810s 5174.353us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1988.020s 32501.722us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 394.900s 7844.508us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 259.790s 4701.918us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1247.800s 20695.177us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 596.300s 7085.984us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 899.870s 12386.813us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1626.360s 26319.301us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 171.970s 3865.463us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 171.150s 3313.478us 0 1 0.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 329.280s 9502.888us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 329.280s 9502.888us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 899.870s 12386.813us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1247.800s 20695.177us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 262.340s 4615.841us 1 1 100.00
chip_sw_pwrmgr_smoketest 240.290s 5493.036us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 190.160s 3603.236us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 199.500s 5041.965us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 237.270s 4287.260us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 964.570s 9329.715us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 159.570s 2897.157us 1 1 100.00
chip_sw_rstmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 171.150s 3313.478us 0 1 0.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 967.770s 7663.100us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 440.810s 4368.599us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 457.270s 5162.642us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 181.730s 2890.397us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 178.260s 2444.891us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 199.500s 5041.965us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 199.500s 5041.965us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 583.330s 9274.920us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 827.170s 12679.706us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 190.160s 3603.236us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 165.270s 3063.416us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 256.310s 5717.455us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 131.740s 3195.415us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 87.350s 3893.046us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 498.470s 5187.110us 1 1 100.00
chip_plic_all_irqs_10 223.850s 3567.373us 1 1 100.00
chip_plic_all_irqs_20 361.660s 4431.198us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 122.370s 2903.320us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 158.270s 3057.135us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2387.620s 14273.424us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 520.610s 8299.168us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 156.740s 2610.001us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 208.890s 3287.874us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 155.680s 2702.553us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 328.950s 4386.516us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 301.810s 3986.528us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 373.150s 6773.278us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 408.510s 8327.047us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 410.560s 7712.975us 1 1 100.00
chip_sw_sram_lc_escalation 1 2 50.00
chip_sw_all_escalation_resets 171.150s 3313.478us 0 1 0.00
chip_sw_data_integrity_escalation 469.130s 6046.027us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 596.300s 7085.984us 1 1 100.00
chip_sw_sysrst_ctrl_reset 936.460s 21499.487us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 141.890s 2646.662us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 238.200s 4412.107us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 319.450s 3899.906us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 936.460s 21499.487us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 936.460s 21499.487us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 629.220s 11122.543us 0 1 0.00
chip_sw_sysrst_ctrl_flash_wp_l 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 629.220s 11122.543us 0 1 0.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 218.980s 6432.304us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3062.970s 34593.272us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 137.700s 2847.719us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 145.080s 3320.668us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 255.140s 4178.591us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 320.900s 4149.162us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1076.730s 8175.972us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4913.740s 31495.474us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1640.800s 11593.038us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 120.700s 2733.691us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 202.110s 2973.915us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 68.800s 2534.604us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9340.280s 72140.607us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 999.800s 6292.298us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 181.740s 4169.630us 0 1 0.00
rom_e2e_jtag_debug_dev 335.680s 5154.261us 0 1 0.00
rom_e2e_jtag_debug_rma 153.790s 3150.907us 0 1 0.00
rom_e2e_jtag_inject 1 3 33.33
rom_e2e_jtag_inject_test_unlocked0 55.520s 1991.647us 0 1 0.00
rom_e2e_jtag_inject_dev 233.400s 5574.339us 1 1 100.00
rom_e2e_jtag_inject_rma 59.170s 2309.853us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 11.299s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 1 1 100.00
chip_sw_clkmgr_jitter_frequency 524.310s 5207.850us 1 1 100.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 308.150s 3065.792us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 1185.350s 7301.491us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1232.890s 8232.856us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 215.400s 1994.154us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 549.570s 4624.129us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 117.130s 2794.666us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 188.180s 3567.000us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 279.660s 6094.704us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 267.400s 5568.711us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 899.870s 12386.813us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 181.740s 4169.630us 0 1 0.00
rom_e2e_jtag_debug_dev 335.680s 5154.261us 0 1 0.00
rom_e2e_jtag_debug_rma 153.790s 3150.907us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 379.620s 5380.722us 1 1 100.00
chip_sw_plic_alerts 0 1 0.00
chip_sw_all_escalation_resets 171.150s 3313.478us 0 1 0.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5463.200s 38533.118us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5463.200s 38533.118us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 162.910s 3678.685us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 401.210s 4462.678us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3054.460s 19598.352us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 5 8 62.50
chip_sival_flash_info_access 179.300s 2931.362us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 385.890s 5209.709us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 90.810s 3118.049us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 110.590s 3059.733us 1 1 100.00
chip_sw_otp_ctrl_descrambling 164.830s 2821.922us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 211.940s 4189.401us 0 1 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.962s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 206.680s 3789.914us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33304) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 56853804014175238959563437304545308797691796058761992427855560101897327305560 214
UVM_ERROR @ 2448.127561 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33304) { a_addr: 'h10348 a_data: 'h6884861f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h24 a_opcode: 'h4 a_user: 'h1b694 d_param: 'h0 d_source: 'h24 d_data: 'h13 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd7d a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2448.127561 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 42980470365334644131209809654631580902776740114980118288164330572568400379707 222
UVM_ERROR @ 3893.045721 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10458 read out mismatch
UVM_INFO @ 3893.045721 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31724) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 92485613137176940841315462592817636127738234543094231892438186771101768247776 221
UVM_ERROR @ 2940.739886 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31724) { a_addr: 'h105bc a_data: 'he6e89305 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2b a_opcode: 'h4 a_user: 'h1864e d_param: 'h0 d_source: 'h2b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2940.739886 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got *
chip_sw_all_escalation_resets 90930092383537297531760720662171417172339485956030894845121008806492489431484 460
UVM_ERROR @ 3313.478304 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3313.478304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 59330722855315702879623060014657296486787750855120990748561753992621562311408 410
UVM_ERROR @ 2610.001412 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 2610.001412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 88227683379599649781489278423315858575276458296004836462788090940569754238280 424
UVM_ERROR @ 6434.206429 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 6434.206429 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 43173917472695261820945222549875060929308209891476206485282802826042419831960 405
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3566.999960 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3566.999960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 63145559724636262055047634473686383139944015946579995400620551141796903107475 394
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2756.780940 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2756.780940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access
chip_sw_otp_ctrl_rot_auth_config 66341389269506345622190095474559069688317001977383444558444598367717676975979 415
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 18335625323463636254395144005532443784913488584042637896800949065636005264182 414
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 48495625989818446135275978617511148177881013406203788711694418861040052783667 456
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 60874730173603929881507028347455444111718548670121019624981855220096147092758 483
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 107966376405035718912389974417465771332147288853497138694069873183533345489272 438
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 97891397773283224378502285957343785563230937096540653489219364376715114885994 458
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 54811613701023930152664782503888800702353611531385030405994858881510060539354 452
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@85412) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 89248076609333016396195835534191559378887037546210990031465634044792111704381 414
UVM_ERROR @ 5041.965376 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@85412) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 5041.965376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 31579861141838879910879295862362833821326286153518987248024659207910766423822 415
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 5896.562500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5896.562500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 11679287003203442595704116440045068114045878347358236093298582749771048216449 420
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 6920.974000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6920.974000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 106734579691015721182216030440377159119529972444072922994893481056008278642833 400
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 8186.616500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8186.616500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
chip_sw_sysrst_ctrl_ec_rst_l 2179382766184720580003335701437850822022010064208818592377237006276545936805 406
UVM_ERROR @ 11122.542960 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
UVM_INFO @ 11122.542960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 105663080559484300908726132092956920742039328268707470508798790791275549629639 413
UVM_ERROR @ 34593.271824 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 34593.271824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!
chip_sw_alert_test 37953897471157320618958879594101361408362315387438414068771797463932788422064 389
UVM_ERROR @ 3209.460988 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
UVM_INFO @ 3209.460988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 11647264510880622972526777253701668464743980083956955480801476409093658953092 391
UVM_ERROR @ 2898.048316 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2898.048316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 54239946469328254073671884082957928142911847738711299685520955898011323942885 None
Job timed out after 240 minutes
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()
chip_sw_pwrmgr_lowpower_cancel 21310121728834872998979415307218421905504174176564954846573629463853658423788 411
UVM_ERROR @ 4189.401352 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
UVM_INFO @ 4189.401352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 2108053004372484771073350473194003935468555355428408931210201334290216060851 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.182s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
rom_e2e_self_hash 37716927345451057291953236613009236588181292000358536321808351001805414068696 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
INFO: Elapsed time: 0.194s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 8398523037566641612398126031097186166224355820619681255130008930630368442977 399
UVM_ERROR @ 3535.732500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3535.732500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 35537838532697975138405208959688729030558615618443245691433641917935618327185 403
UVM_ERROR @ 3906.305000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3906.305000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
chip_sw_ast_clk_rst_inputs 62568210741575601658501434417191959109761007117357595063961248955380323954352 414
UVM_ERROR @ 13562.860325 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
UVM_INFO @ 13562.860325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 17348881830819093838896437114137296645023426891087277965163252457111461169988 472
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 83914582254882669846099691013726037222280152578881334025126509906746011611962 477
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 31861831217466361422099891311990637799834802265319379502978735306681826735512 476
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 111909400352643785858027581366210672536105183858506696320792216157327818440316 495
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 24587493514301328959109081457791770396911085941219664420797654798399105313830 500
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 52062538807813816855387933445993353262668735845276906261498200855098716548481 497
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 111114625665837563048533986550922427439941621221641454062784503026347158340147 499
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 26753286433122702210058010887839417506299167450140967557165814025290745676697 507
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 50792003820766268509117556013464872778998663723205551841740755028445160532078 471
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 47512935105024429029115646646346513222340393402043887033495343338949987820576 473
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 83415719387743025895012307056027482600454314901939165297619380023351993173523 542
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 98282379349422397723460789155935499623295740755125335051365311273895017092239 555
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 110965443476941470709572921204277464482185837236525786639894163833386739329678 592
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 78872042781118684427200395048255927993660914010435622812015187703080943879422 511
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 88764725637375804569176543008641083597739732129084342419304682029623060067994 501
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 19637952137407046059879364188006808951192609384352408380982665224289952188712 493
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 85947558137017958258266077183528361737091073101234833980670474725884110221935 521
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 78180396207068806988898040771831029565115607215878547907113661219078695846354 458
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 82810197760171940696464950650681326355799960248940004533343976506362156904411 550
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 61238662447655086128798275883695372748205179578157805936015837610695876347689 526
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 114918403883817370295364169587344997476601546522283907485230413829421510203014 501
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 86378604702892763997905999849053394859622250426754469691781931997155285486508 485
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 61007821474008863278125148916430511294121917307287825583045795308827246332270 460
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 93234987142099188189149087031712920068334478984256982607128520770523649963973 473
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 73657851463829986919724885387998122424588961742555186429230140491509853675263 477
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_no_meas 71791926477221739215661717699973927920193259547288583335597236557785929160853 410
UVM_ERROR @ 15297.231488 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 15297.231488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_invalid_meas 109626277228301200364763366976791595796645154707241522518019216186139360238074 415
UVM_ERROR @ 16660.361852 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 16660.361852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---