Simulation Results: clkmgr

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.29 %
  • code
  • 98.25 %
  • assert
  • 95.34 %
  • func
  • 86.28 %
  • line
  • 98.98 %
  • branch
  • 98.59 %
  • cond
  • 94.51 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
85.71%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.780s 31.171us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.710s 41.698us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.720s 19.591us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 6.070s 1319.316us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.950s 71.196us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.070s 79.082us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.720s 19.591us 1 1 100.00
clkmgr_csr_aliasing 0.950s 71.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.700s 20.360us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.700s 47.104us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.840s 59.028us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.640s 15.999us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.780s 31.171us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 3.150s 560.697us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.500s 2221.140us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 3.150s 560.697us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 7.570s 2715.786us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.700s 17.758us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.640s 218.770us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.640s 218.770us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.710s 41.698us 1 1 100.00
clkmgr_csr_rw 0.720s 19.591us 1 1 100.00
clkmgr_csr_aliasing 0.950s 71.196us 1 1 100.00
clkmgr_same_csr_outstanding 1.290s 172.819us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.710s 41.698us 1 1 100.00
clkmgr_csr_rw 0.720s 19.591us 1 1 100.00
clkmgr_csr_aliasing 0.950s 71.196us 1 1 100.00
clkmgr_same_csr_outstanding 1.290s 172.819us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.810s 25.702us 0 1 0.00
clkmgr_tl_intg_err 1.240s 61.271us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.610s 123.446us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.610s 123.446us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.610s 123.446us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.610s 123.446us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.440s 152.394us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.240s 61.271us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 3.150s 560.697us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.500s 2221.140us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.610s 123.446us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.800s 30.327us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.770s 42.786us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.720s 46.542us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.790s 42.337us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.830s 58.496us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.720s 19.591us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.810s 25.702us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.720s 19.591us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.720s 19.591us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.810s 25.702us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.340s 1264.217us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 22.940s 2489.988us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 95514883218327246699956878006647527910273616362186632384016112646312554491193 92
UVM_ERROR @ 25701652 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 25701652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---