Simulation Results: edn

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.20 %
  • code
  • 78.65 %
  • assert
  • 94.79 %
  • func
  • 79.17 %
  • line
  • 96.85 %
  • branch
  • 89.40 %
  • cond
  • 85.26 %
  • toggle
  • 74.95 %
  • FSM
  • 46.77 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.890s 30.391us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.990s 147.267us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.190s 14.920us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.730s 358.977us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.240s 63.916us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.010s 25.184us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.190s 14.920us 1 1 100.00
edn_csr_aliasing 1.240s 63.916us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.280s 35.494us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.280s 35.494us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.280s 35.494us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.150s 28.087us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.110s 81.797us 1 1 100.00
errs 1 1 100.00
edn_err 1.270s 19.020us 1 1 100.00
disable 2 2 100.00
edn_disable 0.960s 12.886us 1 1 100.00
edn_disable_auto_req_mode 0.980s 119.275us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.550s 401.167us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.910s 15.290us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.020s 24.411us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.490s 46.110us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.490s 46.110us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.990s 147.267us 1 1 100.00
edn_csr_rw 1.190s 14.920us 1 1 100.00
edn_csr_aliasing 1.240s 63.916us 1 1 100.00
edn_same_csr_outstanding 1.050s 164.279us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.990s 147.267us 1 1 100.00
edn_csr_rw 1.190s 14.920us 1 1 100.00
edn_csr_aliasing 1.240s 63.916us 1 1 100.00
edn_same_csr_outstanding 1.050s 164.279us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.460s 490.232us 1 1 100.00
edn_tl_intg_err 1.910s 86.108us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.160s 29.942us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.110s 81.797us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.460s 490.232us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.460s 490.232us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.460s 490.232us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.460s 490.232us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.110s 81.797us 1 1 100.00
edn_sec_cm 3.460s 490.232us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.110s 81.797us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.910s 86.108us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 68.360s 3737.717us 1 1 100.00

Error Messages

   Test seed line log context