Simulation Results: edn

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.25 %
  • code
  • 84.48 %
  • assert
  • 96.61 %
  • func
  • 80.67 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 89.77 %
  • toggle
  • 95.70 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.820s 29.276us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.920s 18.015us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.910s 46.238us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.420s 58.843us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.260s 26.619us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.800s 26.490us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.910s 46.238us 1 1 100.00
edn_csr_aliasing 1.260s 26.619us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.460s 124.805us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.460s 124.805us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.460s 124.805us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.850s 25.226us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.010s 43.806us 1 1 100.00
errs 1 1 100.00
edn_err 0.910s 28.506us 1 1 100.00
disable 2 2 100.00
edn_disable 0.710s 24.092us 1 1 100.00
edn_disable_auto_req_mode 1.400s 58.967us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.370s 64.909us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.930s 25.701us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.880s 46.513us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.090s 212.848us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.090s 212.848us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.920s 18.015us 1 1 100.00
edn_csr_rw 0.910s 46.238us 1 1 100.00
edn_csr_aliasing 1.260s 26.619us 1 1 100.00
edn_same_csr_outstanding 1.110s 21.587us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.920s 18.015us 1 1 100.00
edn_csr_rw 0.910s 46.238us 1 1 100.00
edn_csr_aliasing 1.260s 26.619us 1 1 100.00
edn_same_csr_outstanding 1.110s 21.587us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.150s 488.983us 1 1 100.00
edn_sec_cm 2.320s 342.163us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.930s 19.263us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.010s 43.806us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.320s 342.163us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.320s 342.163us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.320s 342.163us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.320s 342.163us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.010s 43.806us 1 1 100.00
edn_sec_cm 2.320s 342.163us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.010s 43.806us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.150s 488.983us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 83.990s 20915.395us 1 1 100.00

Error Messages

   Test seed line log context