Simulation Results: flash_ctrl

 
15/12/2025 19:17:40 sha: f063a18 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.20 %
  • code
  • 94.17 %
  • assert
  • 95.64 %
  • func
  • 95.79 %
  • line
  • 95.95 %
  • branch
  • 97.08 %
  • cond
  • 93.71 %
  • toggle
  • 98.41 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
98.46%
V2S
97.73%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 57.970s 36.020us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 10.650s 27.407us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 14.140s 85.333us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.590s 152.690us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 24.920s 1342.000us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 21.720s 2163.082us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.720s 147.040us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.590s 152.690us 1 1 100.00
flash_ctrl_csr_aliasing 21.720s 2163.082us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.670s 32.205us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 8.800s 70.744us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.930s 46.593us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 14.840s 48.997us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1240.860s 104279.147us 1 1 100.00
flash_ctrl_hw_rma_reset 502.210s 130171.993us 1 1 100.00
flash_ctrl_lcmgr_intg 5.660s 37.566us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1713.280s 234473.570us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 375.660s 5318.317us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.950s 133.476us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 3070.670s 203468.458us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 100.050s 5644.829us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.430s 101.507us 1 1 100.00
flash_ctrl_rw_evict_all_en 16.860s 29.835us 1 1 100.00
flash_ctrl_re_evict 16.110s 180.290us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 189.610s 7687.921us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 189.610s 7687.921us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 287.470s 42306.323us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 14.660s 1816.373us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 141.780s 185.606us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 593.200s 12906.272us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 309.480s 10006.466us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 816.470s 3642.278us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.580s 81.297us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 134.660s 1954.726us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.370s 71.742us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.760s 33.473us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 223.870s 279.230us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 138.210s 10037.389us 1 1 100.00
flash_ctrl_otp_reset 51.030s 54.983us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1240.860s 104279.147us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 90.330s 2244.435us 1 1 100.00
flash_ctrl_intr_wr 41.830s 1723.968us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 169.270s 23369.233us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 116.510s 22656.240us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 47.350s 920.712us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 32.930s 644.136us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.830s 65.374us 1 1 100.00
flash_ctrl_ro_derr 91.280s 650.259us 1 1 100.00
flash_ctrl_rw_derr 113.480s 8920.451us 1 1 100.00
flash_ctrl_derr_detect 105.460s 2947.474us 1 1 100.00
flash_ctrl_integrity 422.600s 28809.763us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.770s 49.069us 1 1 100.00
flash_ctrl_ro_serr 86.790s 1219.432us 1 1 100.00
flash_ctrl_rw_serr 153.170s 3327.755us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 60.840s 15953.755us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 77.740s 6515.215us 1 1 100.00
scramble 4 5 80.00
flash_ctrl_wo 160.320s 5848.899us 1 1 100.00
flash_ctrl_write_word_sweep 6.640s 150.470us 1 1 100.00
flash_ctrl_read_word_sweep 10.670s 90.936us 1 1 100.00
flash_ctrl_ro 79.360s 1962.562us 1 1 100.00
flash_ctrl_rw 0.000s 0.000us 0 1 0.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 24.990s 1768.867us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 667.100s 167240.832us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 38.750s 10089.596us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.650s 160.872us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.650s 18.110us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.430s 67.216us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.430s 67.216us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 14.140s 85.333us 1 1 100.00
flash_ctrl_csr_rw 8.590s 152.690us 1 1 100.00
flash_ctrl_csr_aliasing 21.720s 2163.082us 1 1 100.00
flash_ctrl_same_csr_outstanding 14.040s 65.554us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 14.140s 85.333us 1 1 100.00
flash_ctrl_csr_rw 8.590s 152.690us 1 1 100.00
flash_ctrl_csr_aliasing 21.720s 2163.082us 1 1 100.00
flash_ctrl_same_csr_outstanding 14.040s 65.554us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 35.150s 29.140us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 35.150s 29.140us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 35.150s 29.140us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 35.150s 29.140us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 43.320s 1543.705us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 366.760s 509.041us 1 1 100.00
flash_ctrl_sec_cm 1518.740s 846.875us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 366.760s 509.041us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 366.760s 509.041us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 13.790s 65.660us 1 1 100.00
flash_ctrl_wr_intg 7.170s 47.616us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 57.970s 36.020us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 51.030s 54.983us 1 1 100.00
flash_ctrl_disable 10.370s 71.742us 1 1 100.00
flash_ctrl_sec_info_access 38.300s 6564.192us 1 1 100.00
flash_ctrl_connect 6.760s 33.473us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.980s 22.558us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.590s 152.690us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 35.150s 29.140us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.590s 152.690us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 35.150s 29.140us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.590s 152.690us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 35.150s 29.140us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.370s 71.742us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 13.790s 65.660us 1 1 100.00
flash_ctrl_access_after_disable 5.760s 66.212us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.480s 39.159us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.370s 71.742us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 14.660s 1816.373us 1 1 100.00
sec_cm_mem_scramble 0 1 0.00
flash_ctrl_rw 0.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 153.170s 3327.755us 1 1 100.00
flash_ctrl_rw_derr 113.480s 8920.451us 1 1 100.00
flash_ctrl_integrity 422.600s 28809.763us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1240.860s 104279.147us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1518.740s 846.875us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1518.740s 846.875us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1518.740s 846.875us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1518.740s 846.875us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 10.140s 877.834us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 7.840s 74.433us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 8.000s 75.374us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1518.740s 846.875us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1518.740s 846.875us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1518.740s 846.875us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 18.380s 52.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 367.760s 2946.311us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes
flash_ctrl_rw 66158820685661578607904161751011818500063886916540232045215047208016781132000 None
Job timed out after 60 minutes